Lines Matching refs:p
37 int r600_dma_cs_next_reloc(struct radeon_cs_parser *p,
186 static int evergreen_surface_check_linear(struct radeon_cs_parser *p, in evergreen_surface_check_linear() argument
197 static int evergreen_surface_check_linear_aligned(struct radeon_cs_parser *p, in evergreen_surface_check_linear_aligned() argument
201 struct evergreen_cs_track *track = p->track; in evergreen_surface_check_linear_aligned()
211 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n", in evergreen_surface_check_linear_aligned()
219 static int evergreen_surface_check_1d(struct radeon_cs_parser *p, in evergreen_surface_check_1d() argument
223 struct evergreen_cs_track *track = p->track; in evergreen_surface_check_1d()
234 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d (%d %d %d)\n", in evergreen_surface_check_1d()
242 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with 8\n", in evergreen_surface_check_1d()
250 static int evergreen_surface_check_2d(struct radeon_cs_parser *p, in evergreen_surface_check_2d() argument
254 struct evergreen_cs_track *track = p->track; in evergreen_surface_check_2d()
277 dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n", in evergreen_surface_check_2d()
284 dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with %d\n", in evergreen_surface_check_2d()
293 static int evergreen_surface_check(struct radeon_cs_parser *p, in evergreen_surface_check() argument
302 return evergreen_surface_check_linear(p, surf, prefix); in evergreen_surface_check()
304 return evergreen_surface_check_linear_aligned(p, surf, prefix); in evergreen_surface_check()
306 return evergreen_surface_check_1d(p, surf, prefix); in evergreen_surface_check()
308 return evergreen_surface_check_2d(p, surf, prefix); in evergreen_surface_check()
310 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n", in evergreen_surface_check()
317 static int evergreen_surface_value_conv_check(struct radeon_cs_parser *p, in evergreen_surface_value_conv_check() argument
329 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n", in evergreen_surface_value_conv_check()
340 dev_warn(p->dev, "%s:%d %s invalid number of banks %d\n", in evergreen_surface_value_conv_check()
350 dev_warn(p->dev, "%s:%d %s invalid bankw %d\n", in evergreen_surface_value_conv_check()
360 dev_warn(p->dev, "%s:%d %s invalid bankh %d\n", in evergreen_surface_value_conv_check()
370 dev_warn(p->dev, "%s:%d %s invalid macro tile aspect %d\n", in evergreen_surface_value_conv_check()
383 dev_warn(p->dev, "%s:%d %s invalid tile split %d\n", in evergreen_surface_value_conv_check()
390 static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned id) in evergreen_cs_track_validate_cb() argument
392 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_cb()
413 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08x)\n", in evergreen_cs_track_validate_cb()
419 r = evergreen_surface_value_conv_check(p, &surf, "cb"); in evergreen_cs_track_validate_cb()
424 r = evergreen_surface_check(p, &surf, "cb"); in evergreen_cs_track_validate_cb()
426 dev_warn(p->dev, "%s:%d cb[%d] invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n", in evergreen_cs_track_validate_cb()
435 dev_warn(p->dev, "%s:%d cb[%d] bo base %ld not aligned with %ld\n", in evergreen_cs_track_validate_cb()
447 volatile u32 *ib = p->ib.ptr; in evergreen_cs_track_validate_cb()
465 if (!evergreen_surface_check(p, &surf, "cb")) { in evergreen_cs_track_validate_cb()
475 dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, " in evergreen_cs_track_validate_cb()
480 dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n", in evergreen_cs_track_validate_cb()
492 static int evergreen_cs_track_validate_htile(struct radeon_cs_parser *p, in evergreen_cs_track_validate_htile() argument
495 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_htile()
499 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n", in evergreen_cs_track_validate_htile()
536 dev_warn(p->dev, "%s:%d invalid num pipes %d\n", in evergreen_cs_track_validate_htile()
549 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n", in evergreen_cs_track_validate_htile()
557 static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p) in evergreen_cs_track_validate_stencil() argument
559 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_stencil()
580 dev_warn(p->dev, "%s:%d stencil invalid format %d\n", in evergreen_cs_track_validate_stencil()
587 r = evergreen_surface_value_conv_check(p, &surf, "stencil"); in evergreen_cs_track_validate_stencil()
592 r = evergreen_surface_check(p, &surf, NULL); in evergreen_cs_track_validate_stencil()
599 r = evergreen_surface_check(p, &surf, "stencil"); in evergreen_cs_track_validate_stencil()
601 dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n", in evergreen_cs_track_validate_stencil()
610 dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n", in evergreen_cs_track_validate_stencil()
616 dev_warn(p->dev, "%s:%d stencil read bo too small (layer size %d, " in evergreen_cs_track_validate_stencil()
621 dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n", in evergreen_cs_track_validate_stencil()
629 dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n", in evergreen_cs_track_validate_stencil()
635 dev_warn(p->dev, "%s:%d stencil write bo too small (layer size %d, " in evergreen_cs_track_validate_stencil()
645 r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby); in evergreen_cs_track_validate_stencil()
654 static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p) in evergreen_cs_track_validate_depth() argument
656 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_validate_depth()
685 dev_warn(p->dev, "%s:%d depth invalid format %d\n", in evergreen_cs_track_validate_depth()
690 r = evergreen_surface_value_conv_check(p, &surf, "depth"); in evergreen_cs_track_validate_depth()
692 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n", in evergreen_cs_track_validate_depth()
698 r = evergreen_surface_check(p, &surf, "depth"); in evergreen_cs_track_validate_depth()
700 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n", in evergreen_cs_track_validate_depth()
708 dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n", in evergreen_cs_track_validate_depth()
714 dev_warn(p->dev, "%s:%d depth read bo too small (layer size %d, " in evergreen_cs_track_validate_depth()
724 dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n", in evergreen_cs_track_validate_depth()
730 dev_warn(p->dev, "%s:%d depth write bo too small (layer size %d, " in evergreen_cs_track_validate_depth()
740 r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby); in evergreen_cs_track_validate_depth()
749 static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p, in evergreen_cs_track_validate_texture() argument
760 texdw[0] = radeon_get_ib_value(p, idx + 0); in evergreen_cs_track_validate_texture()
761 texdw[1] = radeon_get_ib_value(p, idx + 1); in evergreen_cs_track_validate_texture()
762 texdw[2] = radeon_get_ib_value(p, idx + 2); in evergreen_cs_track_validate_texture()
763 texdw[3] = radeon_get_ib_value(p, idx + 3); in evergreen_cs_track_validate_texture()
764 texdw[4] = radeon_get_ib_value(p, idx + 4); in evergreen_cs_track_validate_texture()
765 texdw[5] = radeon_get_ib_value(p, idx + 5); in evergreen_cs_track_validate_texture()
766 texdw[6] = radeon_get_ib_value(p, idx + 6); in evergreen_cs_track_validate_texture()
767 texdw[7] = radeon_get_ib_value(p, idx + 7); in evergreen_cs_track_validate_texture()
788 if (!r600_fmt_is_valid_texture(surf.format, p->family)) { in evergreen_cs_track_validate_texture()
789 dev_warn(p->dev, "%s:%d texture invalid format %d\n", in evergreen_cs_track_validate_texture()
810 dev_warn(p->dev, "%s:%d texture invalid dimension %d\n", in evergreen_cs_track_validate_texture()
815 r = evergreen_surface_value_conv_check(p, &surf, "texture"); in evergreen_cs_track_validate_texture()
821 evergreen_surface_check(p, &surf, NULL); in evergreen_cs_track_validate_texture()
824 r = evergreen_surface_check(p, &surf, "texture"); in evergreen_cs_track_validate_texture()
826 dev_warn(p->dev, "%s:%d texture invalid 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", in evergreen_cs_track_validate_texture()
834 dev_warn(p->dev, "%s:%d texture bo base %ld not aligned with %ld\n", in evergreen_cs_track_validate_texture()
839 dev_warn(p->dev, "%s:%d mipmap bo base %ld not aligned with %ld\n", in evergreen_cs_track_validate_texture()
849 dev_warn(p->dev, "%s:%d texture bo too small (layer size %d, " in evergreen_cs_track_validate_texture()
860 dev_warn(p->dev, "%s:%i got NULL MIP_ADDRESS relocation\n", in evergreen_cs_track_validate_texture()
884 evergreen_surface_check(p, &surf, NULL); in evergreen_cs_track_validate_texture()
891 dev_warn(p->dev, "%s:%d invalid array mode %d\n", in evergreen_cs_track_validate_texture()
898 r = evergreen_surface_check(p, &surf, "mipmap"); in evergreen_cs_track_validate_texture()
909 dev_warn(p->dev, "%s:%d mipmap [%d] bo too small (layer size %d, " in evergreen_cs_track_validate_texture()
916 dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n", in evergreen_cs_track_validate_texture()
928 static int evergreen_cs_track_check(struct radeon_cs_parser *p) in evergreen_cs_track_check() argument
930 struct evergreen_cs_track *track = p->track; in evergreen_cs_track_check()
955 dev_warn(p->dev, "No buffer for streamout %d\n", i); in evergreen_cs_track_check()
977 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n", in evergreen_cs_track_check()
982 r = evergreen_cs_track_validate_cb(p, i); in evergreen_cs_track_check()
995 r = evergreen_cs_track_validate_stencil(p); in evergreen_cs_track_check()
1002 r = evergreen_cs_track_validate_depth(p); in evergreen_cs_track_check()
1021 static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p) in evergreen_cs_packet_parse_vline() argument
1041 return r600_cs_common_vline_parse(p, vline_start_end, vline_status); in evergreen_cs_packet_parse_vline()
1044 static int evergreen_packet0_check(struct radeon_cs_parser *p, in evergreen_packet0_check() argument
1052 r = evergreen_cs_packet_parse_vline(p); in evergreen_packet0_check()
1067 static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p, in evergreen_cs_parse_packet0() argument
1077 r = evergreen_packet0_check(p, pkt, idx, reg); in evergreen_cs_parse_packet0()
1095 static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) in evergreen_cs_check_reg() argument
1097 struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track; in evergreen_cs_check_reg()
1103 if (p->rdev->family >= CHIP_CAYMAN) in evergreen_cs_check_reg()
1110 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in evergreen_cs_check_reg()
1114 if (p->rdev->family >= CHIP_CAYMAN) { in evergreen_cs_check_reg()
1121 ib = p->ib.ptr; in evergreen_cs_check_reg()
1163 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1165 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_check_reg()
1172 track->db_depth_control = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1176 if (p->rdev->family < CHIP_CAYMAN) { in evergreen_cs_check_reg()
1177 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_check_reg()
1183 if (p->rdev->family < CHIP_CAYMAN) { in evergreen_cs_check_reg()
1184 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_check_reg()
1190 track->db_z_info = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1191 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in evergreen_cs_check_reg()
1192 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1194 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_check_reg()
1218 track->db_s_info = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1222 track->db_depth_view = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1226 track->db_depth_size = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1230 track->db_depth_slice = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1234 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1236 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_check_reg()
1240 track->db_z_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1246 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1248 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_check_reg()
1252 track->db_z_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1258 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1260 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_check_reg()
1264 track->db_s_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1270 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1272 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_check_reg()
1276 track->db_s_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1282 track->vgt_strmout_config = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1286 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1293 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1295 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_check_reg()
1300 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in evergreen_cs_check_reg()
1311 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; in evergreen_cs_check_reg()
1315 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1317 dev_warn(p->dev, "missing reloc for CP_COHER_BASE " in evergreen_cs_check_reg()
1323 track->cb_target_mask = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1327 track->cb_shader_mask = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1331 if (p->rdev->family >= CHIP_CAYMAN) { in evergreen_cs_check_reg()
1332 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_check_reg()
1336 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK; in evergreen_cs_check_reg()
1340 if (p->rdev->family < CHIP_CAYMAN) { in evergreen_cs_check_reg()
1341 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_check_reg()
1345 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK; in evergreen_cs_check_reg()
1357 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1365 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1377 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1378 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in evergreen_cs_check_reg()
1379 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1381 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_check_reg()
1395 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1396 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in evergreen_cs_check_reg()
1397 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1399 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_check_reg()
1417 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1425 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1437 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1446 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1458 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1460 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_check_reg()
1464 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in evergreen_cs_check_reg()
1486 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1488 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_check_reg()
1492 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in evergreen_cs_check_reg()
1519 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1521 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); in evergreen_cs_check_reg()
1536 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1538 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); in evergreen_cs_check_reg()
1553 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1564 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1574 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1576 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_check_reg()
1581 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1590 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1592 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_check_reg()
1597 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1603 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1605 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_check_reg()
1609 track->htile_offset = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1616 track->htile_surface = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1721 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1723 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_check_reg()
1730 if (p->rdev->family >= CHIP_CAYMAN) { in evergreen_cs_check_reg()
1731 dev_warn(p->dev, "bad SET_CONFIG_REG " in evergreen_cs_check_reg()
1735 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1737 dev_warn(p->dev, "bad SET_CONFIG_REG " in evergreen_cs_check_reg()
1744 if (p->rdev->family < CHIP_CAYMAN) { in evergreen_cs_check_reg()
1745 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_check_reg()
1749 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_cs_check_reg()
1751 dev_warn(p->dev, "bad SET_CONTEXT_REG " in evergreen_cs_check_reg()
1758 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; in evergreen_cs_check_reg()
1761 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in evergreen_cs_check_reg()
1767 static bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) in evergreen_is_safe_reg() argument
1771 if (p->rdev->family >= CHIP_CAYMAN) in evergreen_is_safe_reg()
1778 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in evergreen_is_safe_reg()
1782 if (p->rdev->family >= CHIP_CAYMAN) { in evergreen_is_safe_reg()
1789 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in evergreen_is_safe_reg()
1793 static int evergreen_packet3_check(struct radeon_cs_parser *p, in evergreen_packet3_check() argument
1805 track = (struct evergreen_cs_track *)p->track; in evergreen_packet3_check()
1806 ib = p->ib.ptr; in evergreen_packet3_check()
1808 idx_value = radeon_get_ib_value(p, idx); in evergreen_packet3_check()
1822 tmp = radeon_get_ib_value(p, idx + 1); in evergreen_packet3_check()
1834 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1863 if (p->rdev->family < CHIP_CAYMAN) { in evergreen_packet3_check()
1880 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1888 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
1893 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
1895 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
1915 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1923 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
1928 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
1930 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
1943 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
1950 radeon_get_ib_value(p, idx+1) + in evergreen_packet3_check()
1951 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
1956 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
1958 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
1968 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
1970 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
1979 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
1981 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
1990 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
1992 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
2001 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
2003 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
2012 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
2014 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
2038 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2067 dev_warn(p->dev, "DRAW_INDIRECT buffer too small %u + %llu > %lu\n", in evergreen_packet3_check()
2072 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
2074 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
2084 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
2086 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
2095 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2101 r = evergreen_cs_track_check(p); in evergreen_packet3_check()
2103 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__); in evergreen_packet3_check()
2116 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2123 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2124 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2141 command = radeon_get_ib_value(p, idx+4); in evergreen_packet3_check()
2143 info = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2170 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2176 tmp = radeon_get_ib_value(p, idx) + in evergreen_packet3_check()
2177 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
2182 dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n", in evergreen_packet3_check()
2208 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2214 tmp = radeon_get_ib_value(p, idx+2) + in evergreen_packet3_check()
2215 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); in evergreen_packet3_check()
2220 dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n", in evergreen_packet3_check()
2240 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || in evergreen_packet3_check()
2241 radeon_get_ib_value(p, idx + 2) != 0) { in evergreen_packet3_check()
2242 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2258 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2264 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + in evergreen_packet3_check()
2265 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2279 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2286 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2287 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2301 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2308 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2309 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2326 r = evergreen_cs_check_reg(p, reg, idx+1+i); in evergreen_packet3_check()
2342 r = evergreen_cs_check_reg(p, reg, idx+1+i); in evergreen_packet3_check()
2365 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) { in evergreen_packet3_check()
2368 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2373 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { in evergreen_packet3_check()
2399 !radeon_cs_packet_next_is_pkt3_nop(p)) { in evergreen_packet3_check()
2405 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2414 r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8)); in evergreen_packet3_check()
2424 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2429 offset = radeon_get_ib_value(p, idx+1+(i*8)+0); in evergreen_packet3_check()
2430 size = radeon_get_ib_value(p, idx+1+(i*8)+1); in evergreen_packet3_check()
2431 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { in evergreen_packet3_check()
2433 dev_warn(p->dev, "vbo resource seems too big for the bo\n"); in evergreen_packet3_check()
2506 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2511 offset = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2512 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_packet3_check()
2525 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2530 offset = radeon_get_ib_value(p, idx+3); in evergreen_packet3_check()
2531 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_packet3_check()
2550 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2555 offset = radeon_get_ib_value(p, idx+0); in evergreen_packet3_check()
2556 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL; in evergreen_packet3_check()
2579 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2584 offset = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2585 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_packet3_check()
2596 reg = radeon_get_ib_value(p, idx+1) << 2; in evergreen_packet3_check()
2597 if (!evergreen_is_safe_reg(p, reg, idx+1)) in evergreen_packet3_check()
2603 r = radeon_cs_packet_next_reloc(p, &reloc, 0); in evergreen_packet3_check()
2608 offset = radeon_get_ib_value(p, idx+3); in evergreen_packet3_check()
2609 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_packet3_check()
2620 reg = radeon_get_ib_value(p, idx+3) << 2; in evergreen_packet3_check()
2621 if (!evergreen_is_safe_reg(p, reg, idx+3)) in evergreen_packet3_check()
2634 int evergreen_cs_parse(struct radeon_cs_parser *p) in evergreen_cs_parse() argument
2641 if (p->track == NULL) { in evergreen_cs_parse()
2647 if (p->rdev->family >= CHIP_CAYMAN) in evergreen_cs_parse()
2648 tmp = p->rdev->config.cayman.tile_config; in evergreen_cs_parse()
2650 tmp = p->rdev->config.evergreen.tile_config; in evergreen_cs_parse()
2704 p->track = track; in evergreen_cs_parse()
2707 r = radeon_cs_packet_parse(p, &pkt, p->idx); in evergreen_cs_parse()
2709 kfree(p->track); in evergreen_cs_parse()
2710 p->track = NULL; in evergreen_cs_parse()
2713 p->idx += pkt.count + 2; in evergreen_cs_parse()
2716 r = evergreen_cs_parse_packet0(p, &pkt); in evergreen_cs_parse()
2721 r = evergreen_packet3_check(p, &pkt); in evergreen_cs_parse()
2725 kfree(p->track); in evergreen_cs_parse()
2726 p->track = NULL; in evergreen_cs_parse()
2730 kfree(p->track); in evergreen_cs_parse()
2731 p->track = NULL; in evergreen_cs_parse()
2734 } while (p->idx < p->chunk_ib->length_dw); in evergreen_cs_parse()
2736 for (r = 0; r < p->ib.length_dw; r++) { in evergreen_cs_parse()
2737 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]); in evergreen_cs_parse()
2741 kfree(p->track); in evergreen_cs_parse()
2742 p->track = NULL; in evergreen_cs_parse()
2755 int evergreen_dma_cs_parse(struct radeon_cs_parser *p) in evergreen_dma_cs_parse() argument
2757 struct radeon_cs_chunk *ib_chunk = p->chunk_ib; in evergreen_dma_cs_parse()
2760 volatile u32 *ib = p->ib.ptr; in evergreen_dma_cs_parse()
2766 if (p->idx >= ib_chunk->length_dw) { in evergreen_dma_cs_parse()
2768 p->idx, ib_chunk->length_dw); in evergreen_dma_cs_parse()
2771 idx = p->idx; in evergreen_dma_cs_parse()
2772 header = radeon_get_ib_value(p, idx); in evergreen_dma_cs_parse()
2779 r = r600_dma_cs_next_reloc(p, &dst_reloc); in evergreen_dma_cs_parse()
2787 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2791 p->idx += count + 7; in evergreen_dma_cs_parse()
2795 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2796 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_dma_cs_parse()
2800 p->idx += count + 3; in evergreen_dma_cs_parse()
2807 dev_warn(p->dev, "DMA write buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2813 r = r600_dma_cs_next_reloc(p, &src_reloc); in evergreen_dma_cs_parse()
2818 r = r600_dma_cs_next_reloc(p, &dst_reloc); in evergreen_dma_cs_parse()
2827 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2828 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2829 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2830 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in evergreen_dma_cs_parse()
2832 dev_warn(p->dev, "DMA L2L, dw src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2837 dev_warn(p->dev, "DMA L2L, dw dst buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2845 p->idx += 5; in evergreen_dma_cs_parse()
2850 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
2852 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2856 dst_offset = radeon_get_ib_value(p, idx + 7); in evergreen_dma_cs_parse()
2857 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
2862 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
2863 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
2867 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2872 dev_warn(p->dev, "DMA L2T, src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2877 dev_warn(p->dev, "DMA L2T, dst buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2881 p->idx += 9; in evergreen_dma_cs_parse()
2886 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2887 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2888 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2889 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in evergreen_dma_cs_parse()
2891 dev_warn(p->dev, "DMA L2L, byte src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2896 dev_warn(p->dev, "DMA L2L, byte dst buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2904 p->idx += 5; in evergreen_dma_cs_parse()
2909 if (p->family < CHIP_CAYMAN) { in evergreen_dma_cs_parse()
2918 p->idx += 9; in evergreen_dma_cs_parse()
2923 r = r600_dma_cs_next_reloc(p, &dst2_reloc); in evergreen_dma_cs_parse()
2928 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2929 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2930 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2931 dst2_offset |= ((u64)(radeon_get_ib_value(p, idx+5) & 0xff)) << 32; in evergreen_dma_cs_parse()
2932 src_offset = radeon_get_ib_value(p, idx+3); in evergreen_dma_cs_parse()
2933 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; in evergreen_dma_cs_parse()
2935 dev_warn(p->dev, "DMA L2L, dw, broadcast src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2940 dev_warn(p->dev, "DMA L2L, dw, broadcast dst buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2945 dev_warn(p->dev, "DMA L2L, dw, broadcast dst2 buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2955 p->idx += 7; in evergreen_dma_cs_parse()
2959 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
2963 r = r600_dma_cs_next_reloc(p, &dst2_reloc); in evergreen_dma_cs_parse()
2968 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2970 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2972 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
2973 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
2975 dev_warn(p->dev, "DMA L2T, frame to fields src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2980 dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2985 dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
2993 p->idx += 10; in evergreen_dma_cs_parse()
2998 if (p->family < CHIP_CAYMAN) { in evergreen_dma_cs_parse()
3003 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3016 p->idx += 12; in evergreen_dma_cs_parse()
3021 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3025 r = r600_dma_cs_next_reloc(p, &dst2_reloc); in evergreen_dma_cs_parse()
3030 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3032 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3034 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3035 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3037 dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3042 dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3047 dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3055 p->idx += 10; in evergreen_dma_cs_parse()
3061 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3063 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3067 dst_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
3068 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3073 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
3074 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3078 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3083 dev_warn(p->dev, "DMA L2T, T2L src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3088 dev_warn(p->dev, "DMA L2T, T2L dst buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3092 p->idx += 9; in evergreen_dma_cs_parse()
3097 if (p->family < CHIP_CAYMAN) { in evergreen_dma_cs_parse()
3103 p->idx += 13; in evergreen_dma_cs_parse()
3108 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3112 r = r600_dma_cs_next_reloc(p, &dst2_reloc); in evergreen_dma_cs_parse()
3117 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3119 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3121 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3122 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3124 dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3129 dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3134 dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3142 p->idx += 10; in evergreen_dma_cs_parse()
3150 r = r600_dma_cs_next_reloc(p, &dst_reloc); in evergreen_dma_cs_parse()
3155 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3156 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16; in evergreen_dma_cs_parse()
3158 dev_warn(p->dev, "DMA constant fill buffer too small (%llu %lu)\n", in evergreen_dma_cs_parse()
3164 p->idx += 4; in evergreen_dma_cs_parse()
3167 p->idx += 1; in evergreen_dma_cs_parse()
3173 } while (p->idx < p->chunk_ib->length_dw); in evergreen_dma_cs_parse()
3175 for (r = 0; r < p->ib->length_dw; r++) { in evergreen_dma_cs_parse()
3176 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]); in evergreen_dma_cs_parse()