2762 	u64 src_offset, dst_offset, dst2_offset;  in evergreen_dma_cs_parse()  local
2787 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2788 				dst_offset <<= 8;  in evergreen_dma_cs_parse()
2795 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2796 				dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2806 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
2808 					 dst_offset, radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
2829 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2830 				dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2836 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
2838 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
2856 					dst_offset = radeon_get_ib_value(p, idx + 7);  in evergreen_dma_cs_parse()
2857 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2867 					dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2868 					dst_offset <<= 8;  in evergreen_dma_cs_parse()
2876 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
2878 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
2888 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2889 				dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2895 				if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
2897 							dst_offset + count, radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
2928 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2929 				dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;  in evergreen_dma_cs_parse()
2939 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
2941 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
2968 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
2969 				dst_offset <<= 8;  in evergreen_dma_cs_parse()
2979 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
2981 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
3030 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3031 				dst_offset <<= 8;  in evergreen_dma_cs_parse()
3041 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
3043 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
3067 					dst_offset = radeon_get_ib_value(p, idx+7);  in evergreen_dma_cs_parse()
3068 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32;  in evergreen_dma_cs_parse()
3078 					dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3079 					dst_offset <<= 8;  in evergreen_dma_cs_parse()
3087 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
3089 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
3117 				dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3118 				dst_offset <<= 8;  in evergreen_dma_cs_parse()
3128 				if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
3130 							dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()
3155 			dst_offset = radeon_get_ib_value(p, idx+1);  in evergreen_dma_cs_parse()
3156 			dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;  in evergreen_dma_cs_parse()
3157 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in evergreen_dma_cs_parse()
3159 					 dst_offset, radeon_bo_size(dst_reloc->robj));  in evergreen_dma_cs_parse()