Lines Matching refs:rlc
4150 if (rdev->rlc.save_restore_obj) { in sumo_rlc_fini()
4151 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); in sumo_rlc_fini()
4154 radeon_bo_unpin(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4155 radeon_bo_unreserve(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4157 radeon_bo_unref(&rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4158 rdev->rlc.save_restore_obj = NULL; in sumo_rlc_fini()
4162 if (rdev->rlc.clear_state_obj) { in sumo_rlc_fini()
4163 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); in sumo_rlc_fini()
4166 radeon_bo_unpin(rdev->rlc.clear_state_obj); in sumo_rlc_fini()
4167 radeon_bo_unreserve(rdev->rlc.clear_state_obj); in sumo_rlc_fini()
4169 radeon_bo_unref(&rdev->rlc.clear_state_obj); in sumo_rlc_fini()
4170 rdev->rlc.clear_state_obj = NULL; in sumo_rlc_fini()
4174 if (rdev->rlc.cp_table_obj) { in sumo_rlc_fini()
4175 r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false); in sumo_rlc_fini()
4178 radeon_bo_unpin(rdev->rlc.cp_table_obj); in sumo_rlc_fini()
4179 radeon_bo_unreserve(rdev->rlc.cp_table_obj); in sumo_rlc_fini()
4181 radeon_bo_unref(&rdev->rlc.cp_table_obj); in sumo_rlc_fini()
4182 rdev->rlc.cp_table_obj = NULL; in sumo_rlc_fini()
4198 src_ptr = rdev->rlc.reg_list; in sumo_rlc_init()
4199 dws = rdev->rlc.reg_list_size; in sumo_rlc_init()
4203 cs_data = rdev->rlc.cs_data; in sumo_rlc_init()
4207 if (rdev->rlc.save_restore_obj == NULL) { in sumo_rlc_init()
4210 NULL, &rdev->rlc.save_restore_obj); in sumo_rlc_init()
4217 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); in sumo_rlc_init()
4222 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM, in sumo_rlc_init()
4223 &rdev->rlc.save_restore_gpu_addr); in sumo_rlc_init()
4225 radeon_bo_unreserve(rdev->rlc.save_restore_obj); in sumo_rlc_init()
4231 r = radeon_bo_kmap(rdev->rlc.save_restore_obj, (void **)&rdev->rlc.sr_ptr); in sumo_rlc_init()
4238 dst_ptr = rdev->rlc.sr_ptr; in sumo_rlc_init()
4241 for (i = 0; i < rdev->rlc.reg_list_size; i++) in sumo_rlc_init()
4261 radeon_bo_kunmap(rdev->rlc.save_restore_obj); in sumo_rlc_init()
4262 radeon_bo_unreserve(rdev->rlc.save_restore_obj); in sumo_rlc_init()
4268 rdev->rlc.clear_state_size = dws = cik_get_csb_size(rdev); in sumo_rlc_init()
4270 rdev->rlc.clear_state_size = si_get_csb_size(rdev); in sumo_rlc_init()
4271 dws = rdev->rlc.clear_state_size + (256 / 4); in sumo_rlc_init()
4283 rdev->rlc.clear_state_size = dws; in sumo_rlc_init()
4286 if (rdev->rlc.clear_state_obj == NULL) { in sumo_rlc_init()
4289 NULL, &rdev->rlc.clear_state_obj); in sumo_rlc_init()
4296 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); in sumo_rlc_init()
4301 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM, in sumo_rlc_init()
4302 &rdev->rlc.clear_state_gpu_addr); in sumo_rlc_init()
4304 radeon_bo_unreserve(rdev->rlc.clear_state_obj); in sumo_rlc_init()
4310 r = radeon_bo_kmap(rdev->rlc.clear_state_obj, (void **)&rdev->rlc.cs_ptr); in sumo_rlc_init()
4317 dst_ptr = rdev->rlc.cs_ptr; in sumo_rlc_init()
4321 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256; in sumo_rlc_init()
4324 dst_ptr[2] = cpu_to_le32(rdev->rlc.clear_state_size); in sumo_rlc_init()
4328 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4); in sumo_rlc_init()
4357 radeon_bo_kunmap(rdev->rlc.clear_state_obj); in sumo_rlc_init()
4358 radeon_bo_unreserve(rdev->rlc.clear_state_obj); in sumo_rlc_init()
4361 if (rdev->rlc.cp_table_size) { in sumo_rlc_init()
4362 if (rdev->rlc.cp_table_obj == NULL) { in sumo_rlc_init()
4363 r = radeon_bo_create(rdev, rdev->rlc.cp_table_size, in sumo_rlc_init()
4366 NULL, &rdev->rlc.cp_table_obj); in sumo_rlc_init()
4374 r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false); in sumo_rlc_init()
4380 r = radeon_bo_pin(rdev->rlc.cp_table_obj, RADEON_GEM_DOMAIN_VRAM, in sumo_rlc_init()
4381 &rdev->rlc.cp_table_gpu_addr); in sumo_rlc_init()
4383 radeon_bo_unreserve(rdev->rlc.cp_table_obj); in sumo_rlc_init()
4388 r = radeon_bo_kmap(rdev->rlc.cp_table_obj, (void **)&rdev->rlc.cp_table_ptr); in sumo_rlc_init()
4397 radeon_bo_kunmap(rdev->rlc.cp_table_obj); in sumo_rlc_init()
4398 radeon_bo_unreserve(rdev->rlc.cp_table_obj); in sumo_rlc_init()
4447 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in evergreen_rlc_resume()
4448 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in evergreen_rlc_resume()
5506 rdev->rlc.reg_list = sumo_rlc_save_restore_register_list; in evergreen_startup()
5507 rdev->rlc.reg_list_size = in evergreen_startup()
5509 rdev->rlc.cs_data = evergreen_cs_data; in evergreen_startup()