140 				     int ring, u32 cp_int_cntl);
2973 	struct radeon_ring *ring = &rdev->ring[ib->ring];  in evergreen_ring_ib_execute()  local
2977 	radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));  in evergreen_ring_ib_execute()
2978 	radeon_ring_write(ring, 1);  in evergreen_ring_ib_execute()
2980 	if (ring->rptr_save_reg) {  in evergreen_ring_ib_execute()
2981 		next_rptr = ring->wptr + 3 + 4;  in evergreen_ring_ib_execute()
2982 		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));  in evergreen_ring_ib_execute()
2983 		radeon_ring_write(ring, ((ring->rptr_save_reg -   in evergreen_ring_ib_execute()
2985 		radeon_ring_write(ring, next_rptr);  in evergreen_ring_ib_execute()
2987 		next_rptr = ring->wptr + 5 + 4;  in evergreen_ring_ib_execute()
2988 		radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));  in evergreen_ring_ib_execute()
2989 		radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);  in evergreen_ring_ib_execute()
2990 		radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));  in evergreen_ring_ib_execute()
2991 		radeon_ring_write(ring, next_rptr);  in evergreen_ring_ib_execute()
2992 		radeon_ring_write(ring, 0);  in evergreen_ring_ib_execute()
2995 	radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));  in evergreen_ring_ib_execute()
2996 	radeon_ring_write(ring,  in evergreen_ring_ib_execute()
3001 	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);  in evergreen_ring_ib_execute()
3002 	radeon_ring_write(ring, ib->length_dw);  in evergreen_ring_ib_execute()
3040 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];  in evergreen_cp_start()  local
3044 	r = radeon_ring_lock(rdev, ring, 7);  in evergreen_cp_start()
3049 	radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));  in evergreen_cp_start()
3050 	radeon_ring_write(ring, 0x1);  in evergreen_cp_start()
3051 	radeon_ring_write(ring, 0x0);  in evergreen_cp_start()
3052 	radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);  in evergreen_cp_start()
3053 	radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));  in evergreen_cp_start()
3054 	radeon_ring_write(ring, 0);  in evergreen_cp_start()
3055 	radeon_ring_write(ring, 0);  in evergreen_cp_start()
3056 	radeon_ring_unlock_commit(rdev, ring, false);  in evergreen_cp_start()
3061 	r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);  in evergreen_cp_start()
3068 	radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in evergreen_cp_start()
3069 	radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);  in evergreen_cp_start()
3072 		radeon_ring_write(ring, evergreen_default_state[i]);  in evergreen_cp_start()
3074 	radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in evergreen_cp_start()
3075 	radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);  in evergreen_cp_start()
3078 	radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));  in evergreen_cp_start()
3079 	radeon_ring_write(ring, 0);  in evergreen_cp_start()
3082 	radeon_ring_write(ring, 0xc0026f00);  in evergreen_cp_start()
3083 	radeon_ring_write(ring, 0x00000000);  in evergreen_cp_start()
3084 	radeon_ring_write(ring, 0x00000000);  in evergreen_cp_start()
3085 	radeon_ring_write(ring, 0x00000000);  in evergreen_cp_start()
3088 	radeon_ring_write(ring, 0xc0036f00);  in evergreen_cp_start()
3089 	radeon_ring_write(ring, 0x00000bc4);  in evergreen_cp_start()
3090 	radeon_ring_write(ring, 0xffffffff);  in evergreen_cp_start()
3091 	radeon_ring_write(ring, 0xffffffff);  in evergreen_cp_start()
3092 	radeon_ring_write(ring, 0xffffffff);  in evergreen_cp_start()
3094 	radeon_ring_write(ring, 0xc0026900);  in evergreen_cp_start()
3095 	radeon_ring_write(ring, 0x00000316);  in evergreen_cp_start()
3096 	radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */  in evergreen_cp_start()
3097 	radeon_ring_write(ring, 0x00000010); /*  */  in evergreen_cp_start()
3099 	radeon_ring_unlock_commit(rdev, ring, false);  in evergreen_cp_start()
3106 	struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];  in evergreen_cp_resume()  local
3124 	rb_bufsz = order_base_2(ring->ring_size / 8);  in evergreen_cp_resume()
3139 	ring->wptr = 0;  in evergreen_cp_resume()
3140 	WREG32(CP_RB_WPTR, ring->wptr);  in evergreen_cp_resume()
3158 	WREG32(CP_RB_BASE, ring->gpu_addr >> 8);  in evergreen_cp_resume()
3162 	ring->ready = true;  in evergreen_cp_resume()
3163 	r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);  in evergreen_cp_resume()
3165 		ring->ready = false;  in evergreen_cp_resume()
4126 bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)  in evergreen_gfx_is_lockup()  argument
4133 		radeon_ring_lockup_update(rdev, ring);  in evergreen_gfx_is_lockup()
4136 	return radeon_ring_test_lockup(rdev, ring);  in evergreen_gfx_is_lockup()
5021 		src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;  in evergreen_irq_process()
5022 		src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;  in evergreen_irq_process()
5472 	struct radeon_ring *ring;  in evergreen_startup()  local
5543 		rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;  in evergreen_startup()
5560 	ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];  in evergreen_startup()
5561 	r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,  in evergreen_startup()
5566 	ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];  in evergreen_startup()
5567 	r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,  in evergreen_startup()
5582 	ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];  in evergreen_startup()
5583 	if (ring->ring_size) {  in evergreen_startup()
5584 		r = radeon_ring_init(rdev, ring, ring->ring_size, 0,  in evergreen_startup()
5742 	rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;  in evergreen_init()
5743 	r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);  in evergreen_init()
5745 	rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;  in evergreen_init()
5746 	r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);  in evergreen_init()
5750 		rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;  in evergreen_init()
5751 		r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX],  in evergreen_init()