Lines Matching refs:rdev
135 static void evergreen_gpu_init(struct radeon_device *rdev);
136 void evergreen_fini(struct radeon_device *rdev);
137 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
138 void evergreen_program_aspm(struct radeon_device *rdev);
139 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
141 extern void cayman_vm_decode_fault(struct radeon_device *rdev,
143 void cik_init_cp_pg_table(struct radeon_device *rdev);
145 extern u32 si_get_csb_size(struct radeon_device *rdev);
146 extern void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer);
147 extern u32 cik_get_csb_size(struct radeon_device *rdev);
148 extern void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer);
149 extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
923 static void evergreen_init_golden_registers(struct radeon_device *rdev) in evergreen_init_golden_registers() argument
925 switch (rdev->family) { in evergreen_init_golden_registers()
928 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
931 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
934 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
939 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
942 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
945 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
950 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
953 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
956 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
961 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
964 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
967 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
972 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
977 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
982 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
985 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
990 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
995 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1000 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1019 int evergreen_get_allowed_info_register(struct radeon_device *rdev, in evergreen_get_allowed_info_register() argument
1068 static int sumo_set_uvd_clock(struct radeon_device *rdev, u32 clock, in sumo_set_uvd_clock() argument
1074 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, in sumo_set_uvd_clock()
1092 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in sumo_set_uvd_clocks() argument
1097 r = sumo_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS); in sumo_set_uvd_clocks()
1103 r = sumo_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS); in sumo_set_uvd_clocks()
1115 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in evergreen_set_uvd_clocks() argument
1135 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000, in evergreen_set_uvd_clocks()
1153 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in evergreen_set_uvd_clocks()
1190 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in evergreen_set_uvd_clocks()
1204 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev) in evergreen_fix_pci_max_read_req_size() argument
1209 readrq = pcie_get_readrq(rdev->pdev); in evergreen_fix_pci_max_read_req_size()
1215 pcie_set_readrq(rdev->pdev, 512); in evergreen_fix_pci_max_read_req_size()
1221 struct radeon_device *rdev = dev->dev_private; in dce4_program_fmt() local
1274 static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc) in dce4_is_in_vblank() argument
1282 static bool dce4_is_counter_moving(struct radeon_device *rdev, int crtc) in dce4_is_counter_moving() argument
1303 void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc) in dce4_wait_for_vblank() argument
1307 if (crtc >= rdev->num_crtc) in dce4_wait_for_vblank()
1316 while (dce4_is_in_vblank(rdev, crtc)) { in dce4_wait_for_vblank()
1318 if (!dce4_is_counter_moving(rdev, crtc)) in dce4_wait_for_vblank()
1323 while (!dce4_is_in_vblank(rdev, crtc)) { in dce4_wait_for_vblank()
1325 if (!dce4_is_counter_moving(rdev, crtc)) in dce4_wait_for_vblank()
1344 void evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) in evergreen_page_flip() argument
1346 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in evergreen_page_flip()
1366 for (i = 0; i < rdev->usec_timeout; i++) { in evergreen_page_flip()
1386 bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc_id) in evergreen_page_flip_pending() argument
1388 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in evergreen_page_flip_pending()
1396 int evergreen_get_temp(struct radeon_device *rdev) in evergreen_get_temp() argument
1401 if (rdev->family == CHIP_JUNIPER) { in evergreen_get_temp()
1434 int sumo_get_temp(struct radeon_device *rdev) in sumo_get_temp() argument
1451 void sumo_pm_init_profile(struct radeon_device *rdev) in sumo_pm_init_profile() argument
1456 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in sumo_pm_init_profile()
1457 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in sumo_pm_init_profile()
1458 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in sumo_pm_init_profile()
1459 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in sumo_pm_init_profile()
1462 if (rdev->flags & RADEON_IS_MOBILITY) in sumo_pm_init_profile()
1463 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); in sumo_pm_init_profile()
1465 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); in sumo_pm_init_profile()
1467 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; in sumo_pm_init_profile()
1468 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; in sumo_pm_init_profile()
1469 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in sumo_pm_init_profile()
1470 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in sumo_pm_init_profile()
1472 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; in sumo_pm_init_profile()
1473 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; in sumo_pm_init_profile()
1474 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in sumo_pm_init_profile()
1475 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in sumo_pm_init_profile()
1477 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; in sumo_pm_init_profile()
1478 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; in sumo_pm_init_profile()
1479 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in sumo_pm_init_profile()
1480 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in sumo_pm_init_profile()
1482 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; in sumo_pm_init_profile()
1483 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; in sumo_pm_init_profile()
1484 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in sumo_pm_init_profile()
1485 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in sumo_pm_init_profile()
1488 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); in sumo_pm_init_profile()
1489 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; in sumo_pm_init_profile()
1490 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; in sumo_pm_init_profile()
1491 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in sumo_pm_init_profile()
1492 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = in sumo_pm_init_profile()
1493 rdev->pm.power_state[idx].num_clock_modes - 1; in sumo_pm_init_profile()
1495 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; in sumo_pm_init_profile()
1496 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; in sumo_pm_init_profile()
1497 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in sumo_pm_init_profile()
1498 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = in sumo_pm_init_profile()
1499 rdev->pm.power_state[idx].num_clock_modes - 1; in sumo_pm_init_profile()
1511 void btc_pm_init_profile(struct radeon_device *rdev) in btc_pm_init_profile() argument
1516 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in btc_pm_init_profile()
1517 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in btc_pm_init_profile()
1518 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in btc_pm_init_profile()
1519 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; in btc_pm_init_profile()
1524 if (rdev->flags & RADEON_IS_MOBILITY) in btc_pm_init_profile()
1525 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); in btc_pm_init_profile()
1527 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); in btc_pm_init_profile()
1529 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; in btc_pm_init_profile()
1530 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; in btc_pm_init_profile()
1531 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in btc_pm_init_profile()
1532 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in btc_pm_init_profile()
1534 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; in btc_pm_init_profile()
1535 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; in btc_pm_init_profile()
1536 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in btc_pm_init_profile()
1537 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; in btc_pm_init_profile()
1539 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; in btc_pm_init_profile()
1540 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; in btc_pm_init_profile()
1541 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in btc_pm_init_profile()
1542 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; in btc_pm_init_profile()
1544 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; in btc_pm_init_profile()
1545 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; in btc_pm_init_profile()
1546 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in btc_pm_init_profile()
1547 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in btc_pm_init_profile()
1549 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; in btc_pm_init_profile()
1550 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; in btc_pm_init_profile()
1551 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in btc_pm_init_profile()
1552 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; in btc_pm_init_profile()
1554 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; in btc_pm_init_profile()
1555 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; in btc_pm_init_profile()
1556 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in btc_pm_init_profile()
1557 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; in btc_pm_init_profile()
1568 void evergreen_pm_misc(struct radeon_device *rdev) in evergreen_pm_misc() argument
1570 int req_ps_idx = rdev->pm.requested_power_state_index; in evergreen_pm_misc()
1571 int req_cm_idx = rdev->pm.requested_clock_mode_index; in evergreen_pm_misc()
1572 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; in evergreen_pm_misc()
1579 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) { in evergreen_pm_misc()
1580 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); in evergreen_pm_misc()
1581 rdev->pm.current_vddc = voltage->voltage; in evergreen_pm_misc()
1589 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && in evergreen_pm_misc()
1590 (rdev->family >= CHIP_BARTS) && in evergreen_pm_misc()
1591 rdev->pm.active_crtc_count && in evergreen_pm_misc()
1592 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || in evergreen_pm_misc()
1593 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) in evergreen_pm_misc()
1594 voltage = &rdev->pm.power_state[req_ps_idx]. in evergreen_pm_misc()
1595 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].voltage; in evergreen_pm_misc()
1600 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) { in evergreen_pm_misc()
1601 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI); in evergreen_pm_misc()
1602 rdev->pm.current_vddci = voltage->vddci; in evergreen_pm_misc()
1615 void evergreen_pm_prepare(struct radeon_device *rdev) in evergreen_pm_prepare() argument
1617 struct drm_device *ddev = rdev->ddev; in evergreen_pm_prepare()
1640 void evergreen_pm_finish(struct radeon_device *rdev) in evergreen_pm_finish() argument
1642 struct drm_device *ddev = rdev->ddev; in evergreen_pm_finish()
1667 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) in evergreen_hpd_sense() argument
1711 void evergreen_hpd_set_polarity(struct radeon_device *rdev, in evergreen_hpd_set_polarity() argument
1715 bool connected = evergreen_hpd_sense(rdev, hpd); in evergreen_hpd_set_polarity()
1779 void evergreen_hpd_init(struct radeon_device *rdev) in evergreen_hpd_init() argument
1781 struct drm_device *dev = rdev->ddev; in evergreen_hpd_init()
1821 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); in evergreen_hpd_init()
1824 radeon_irq_kms_enable_hpd(rdev, enabled); in evergreen_hpd_init()
1835 void evergreen_hpd_fini(struct radeon_device *rdev) in evergreen_hpd_fini() argument
1837 struct drm_device *dev = rdev->ddev; in evergreen_hpd_fini()
1867 radeon_irq_kms_disable_hpd(rdev, disabled); in evergreen_hpd_fini()
1872 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, in evergreen_line_buffer_adjust() argument
1918 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { in evergreen_line_buffer_adjust()
1921 for (i = 0; i < rdev->usec_timeout; i++) { in evergreen_line_buffer_adjust()
1934 if (ASIC_IS_DCE5(rdev)) in evergreen_line_buffer_adjust()
1940 if (ASIC_IS_DCE5(rdev)) in evergreen_line_buffer_adjust()
1946 if (ASIC_IS_DCE5(rdev)) in evergreen_line_buffer_adjust()
1952 if (ASIC_IS_DCE5(rdev)) in evergreen_line_buffer_adjust()
1963 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev) in evergreen_get_number_of_dram_channels() argument
2207 static void evergreen_program_watermarks(struct radeon_device *rdev, in evergreen_program_watermarks() argument
2229 dram_channels = evergreen_get_number_of_dram_channels(rdev); in evergreen_program_watermarks()
2232 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { in evergreen_program_watermarks()
2234 radeon_dpm_get_mclk(rdev, false) * 10; in evergreen_program_watermarks()
2236 radeon_dpm_get_sclk(rdev, false) * 10; in evergreen_program_watermarks()
2238 wm_high.yclk = rdev->pm.current_mclk * 10; in evergreen_program_watermarks()
2239 wm_high.sclk = rdev->pm.current_sclk * 10; in evergreen_program_watermarks()
2259 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { in evergreen_program_watermarks()
2261 radeon_dpm_get_mclk(rdev, true) * 10; in evergreen_program_watermarks()
2263 radeon_dpm_get_sclk(rdev, true) * 10; in evergreen_program_watermarks()
2265 wm_low.yclk = rdev->pm.current_mclk * 10; in evergreen_program_watermarks()
2266 wm_low.sclk = rdev->pm.current_sclk * 10; in evergreen_program_watermarks()
2295 (rdev->disp_priority == 2)) { in evergreen_program_watermarks()
2302 (rdev->disp_priority == 2)) { in evergreen_program_watermarks()
2370 void evergreen_bandwidth_update(struct radeon_device *rdev) in evergreen_bandwidth_update() argument
2377 if (!rdev->mode_info.mode_config_initialized) in evergreen_bandwidth_update()
2380 radeon_update_display_priority(rdev); in evergreen_bandwidth_update()
2382 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_bandwidth_update()
2383 if (rdev->mode_info.crtcs[i]->base.enabled) in evergreen_bandwidth_update()
2386 for (i = 0; i < rdev->num_crtc; i += 2) { in evergreen_bandwidth_update()
2387 mode0 = &rdev->mode_info.crtcs[i]->base.mode; in evergreen_bandwidth_update()
2388 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; in evergreen_bandwidth_update()
2389 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); in evergreen_bandwidth_update()
2390 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); in evergreen_bandwidth_update()
2391 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); in evergreen_bandwidth_update()
2392 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads); in evergreen_bandwidth_update()
2405 int evergreen_mc_wait_for_idle(struct radeon_device *rdev) in evergreen_mc_wait_for_idle() argument
2410 for (i = 0; i < rdev->usec_timeout; i++) { in evergreen_mc_wait_for_idle()
2423 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev) in evergreen_pcie_gart_tlb_flush() argument
2431 for (i = 0; i < rdev->usec_timeout; i++) { in evergreen_pcie_gart_tlb_flush()
2446 static int evergreen_pcie_gart_enable(struct radeon_device *rdev) in evergreen_pcie_gart_enable() argument
2451 if (rdev->gart.robj == NULL) { in evergreen_pcie_gart_enable()
2452 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in evergreen_pcie_gart_enable()
2455 r = radeon_gart_table_vram_pin(rdev); in evergreen_pcie_gart_enable()
2469 if (rdev->flags & RADEON_IS_IGP) { in evergreen_pcie_gart_enable()
2477 if ((rdev->family == CHIP_JUNIPER) || in evergreen_pcie_gart_enable()
2478 (rdev->family == CHIP_CYPRESS) || in evergreen_pcie_gart_enable()
2479 (rdev->family == CHIP_HEMLOCK) || in evergreen_pcie_gart_enable()
2480 (rdev->family == CHIP_BARTS)) in evergreen_pcie_gart_enable()
2487 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in evergreen_pcie_gart_enable()
2488 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in evergreen_pcie_gart_enable()
2489 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in evergreen_pcie_gart_enable()
2493 (u32)(rdev->dummy_page.addr >> 12)); in evergreen_pcie_gart_enable()
2496 evergreen_pcie_gart_tlb_flush(rdev); in evergreen_pcie_gart_enable()
2498 (unsigned)(rdev->mc.gtt_size >> 20), in evergreen_pcie_gart_enable()
2499 (unsigned long long)rdev->gart.table_addr); in evergreen_pcie_gart_enable()
2500 rdev->gart.ready = true; in evergreen_pcie_gart_enable()
2504 static void evergreen_pcie_gart_disable(struct radeon_device *rdev) in evergreen_pcie_gart_disable() argument
2526 radeon_gart_table_vram_unpin(rdev); in evergreen_pcie_gart_disable()
2529 static void evergreen_pcie_gart_fini(struct radeon_device *rdev) in evergreen_pcie_gart_fini() argument
2531 evergreen_pcie_gart_disable(rdev); in evergreen_pcie_gart_fini()
2532 radeon_gart_table_vram_free(rdev); in evergreen_pcie_gart_fini()
2533 radeon_gart_fini(rdev); in evergreen_pcie_gart_fini()
2537 static void evergreen_agp_enable(struct radeon_device *rdev) in evergreen_agp_enable() argument
2604 static bool evergreen_is_dp_sst_stream_enabled(struct radeon_device *rdev, in evergreen_is_dp_sst_stream_enabled() argument
2664 static void evergreen_blank_dp_output(struct radeon_device *rdev, in evergreen_blank_dp_output() argument
2704 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) in evergreen_mc_stop() argument
2710 if (!ASIC_IS_NODCE(rdev)) { in evergreen_mc_stop()
2718 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_mc_stop()
2722 if (ASIC_IS_DCE6(rdev)) { in evergreen_mc_stop()
2725 radeon_wait_for_vblank(rdev, i); in evergreen_mc_stop()
2734 radeon_wait_for_vblank(rdev, i); in evergreen_mc_stop()
2742 frame_count = radeon_get_vblank_counter(rdev, i); in evergreen_mc_stop()
2743 for (j = 0; j < rdev->usec_timeout; j++) { in evergreen_mc_stop()
2744 if (radeon_get_vblank_counter(rdev, i) != frame_count) in evergreen_mc_stop()
2755 if (ASIC_IS_DCE5(rdev) && in evergreen_mc_stop()
2756 evergreen_is_dp_sst_stream_enabled(rdev, i ,&dig_fe)) in evergreen_mc_stop()
2757 evergreen_blank_dp_output(rdev, dig_fe); in evergreen_mc_stop()
2772 radeon_mc_wait_for_idle(rdev); in evergreen_mc_stop()
2786 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_mc_stop()
2802 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) in evergreen_mc_resume() argument
2808 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_mc_resume()
2810 upper_32_bits(rdev->mc.vram_start)); in evergreen_mc_resume()
2812 upper_32_bits(rdev->mc.vram_start)); in evergreen_mc_resume()
2814 (u32)rdev->mc.vram_start); in evergreen_mc_resume()
2816 (u32)rdev->mc.vram_start); in evergreen_mc_resume()
2819 if (!ASIC_IS_NODCE(rdev)) { in evergreen_mc_resume()
2820 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); in evergreen_mc_resume()
2821 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); in evergreen_mc_resume()
2825 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_mc_resume()
2843 for (j = 0; j < rdev->usec_timeout; j++) { in evergreen_mc_resume()
2859 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_mc_resume()
2861 if (ASIC_IS_DCE6(rdev)) { in evergreen_mc_resume()
2875 frame_count = radeon_get_vblank_counter(rdev, i); in evergreen_mc_resume()
2876 for (j = 0; j < rdev->usec_timeout; j++) { in evergreen_mc_resume()
2877 if (radeon_get_vblank_counter(rdev, i) != frame_count) in evergreen_mc_resume()
2883 if (!ASIC_IS_NODCE(rdev)) { in evergreen_mc_resume()
2891 void evergreen_mc_program(struct radeon_device *rdev) in evergreen_mc_program() argument
2907 evergreen_mc_stop(rdev, &save); in evergreen_mc_program()
2908 if (evergreen_mc_wait_for_idle(rdev)) { in evergreen_mc_program()
2909 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in evergreen_mc_program()
2914 if (rdev->flags & RADEON_IS_AGP) { in evergreen_mc_program()
2915 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in evergreen_mc_program()
2918 rdev->mc.vram_start >> 12); in evergreen_mc_program()
2920 rdev->mc.gtt_end >> 12); in evergreen_mc_program()
2924 rdev->mc.gtt_start >> 12); in evergreen_mc_program()
2926 rdev->mc.vram_end >> 12); in evergreen_mc_program()
2930 rdev->mc.vram_start >> 12); in evergreen_mc_program()
2932 rdev->mc.vram_end >> 12); in evergreen_mc_program()
2934 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in evergreen_mc_program()
2936 if ((rdev->family == CHIP_PALM) || in evergreen_mc_program()
2937 (rdev->family == CHIP_SUMO) || in evergreen_mc_program()
2938 (rdev->family == CHIP_SUMO2)) { in evergreen_mc_program()
2940 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24; in evergreen_mc_program()
2941 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20; in evergreen_mc_program()
2944 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in evergreen_mc_program()
2945 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in evergreen_mc_program()
2947 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in evergreen_mc_program()
2950 if (rdev->flags & RADEON_IS_AGP) { in evergreen_mc_program()
2951 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); in evergreen_mc_program()
2952 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); in evergreen_mc_program()
2953 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); in evergreen_mc_program()
2959 if (evergreen_mc_wait_for_idle(rdev)) { in evergreen_mc_program()
2960 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in evergreen_mc_program()
2962 evergreen_mc_resume(rdev, &save); in evergreen_mc_program()
2965 rv515_vga_render_disable(rdev); in evergreen_mc_program()
2971 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) in evergreen_ring_ib_execute() argument
2973 struct radeon_ring *ring = &rdev->ring[ib->ring]; in evergreen_ring_ib_execute()
2986 } else if (rdev->wb.enabled) { in evergreen_ring_ib_execute()
3006 static int evergreen_cp_load_microcode(struct radeon_device *rdev) in evergreen_cp_load_microcode() argument
3011 if (!rdev->me_fw || !rdev->pfp_fw) in evergreen_cp_load_microcode()
3014 r700_cp_stop(rdev); in evergreen_cp_load_microcode()
3021 fw_data = (const __be32 *)rdev->pfp_fw->data; in evergreen_cp_load_microcode()
3027 fw_data = (const __be32 *)rdev->me_fw->data; in evergreen_cp_load_microcode()
3038 static int evergreen_cp_start(struct radeon_device *rdev) in evergreen_cp_start() argument
3040 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in evergreen_cp_start()
3044 r = radeon_ring_lock(rdev, ring, 7); in evergreen_cp_start()
3052 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1); in evergreen_cp_start()
3056 radeon_ring_unlock_commit(rdev, ring, false); in evergreen_cp_start()
3061 r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19); in evergreen_cp_start()
3099 radeon_ring_unlock_commit(rdev, ring, false); in evergreen_cp_start()
3104 static int evergreen_cp_resume(struct radeon_device *rdev) in evergreen_cp_resume() argument
3106 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in evergreen_cp_resume()
3144 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); in evergreen_cp_resume()
3145 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in evergreen_cp_resume()
3146 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in evergreen_cp_resume()
3148 if (rdev->wb.enabled) in evergreen_cp_resume()
3161 evergreen_cp_start(rdev); in evergreen_cp_resume()
3163 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); in evergreen_cp_resume()
3174 static void evergreen_gpu_init(struct radeon_device *rdev) in evergreen_gpu_init() argument
3195 switch (rdev->family) { in evergreen_gpu_init()
3198 rdev->config.evergreen.num_ses = 2; in evergreen_gpu_init()
3199 rdev->config.evergreen.max_pipes = 4; in evergreen_gpu_init()
3200 rdev->config.evergreen.max_tile_pipes = 8; in evergreen_gpu_init()
3201 rdev->config.evergreen.max_simds = 10; in evergreen_gpu_init()
3202 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3203 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3204 rdev->config.evergreen.max_threads = 248; in evergreen_gpu_init()
3205 rdev->config.evergreen.max_gs_threads = 32; in evergreen_gpu_init()
3206 rdev->config.evergreen.max_stack_entries = 512; in evergreen_gpu_init()
3207 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3208 rdev->config.evergreen.sx_max_export_size = 256; in evergreen_gpu_init()
3209 rdev->config.evergreen.sx_max_export_pos_size = 64; in evergreen_gpu_init()
3210 rdev->config.evergreen.sx_max_export_smx_size = 192; in evergreen_gpu_init()
3211 rdev->config.evergreen.max_hw_contexts = 8; in evergreen_gpu_init()
3212 rdev->config.evergreen.sq_num_cf_insts = 2; in evergreen_gpu_init()
3214 rdev->config.evergreen.sc_prim_fifo_size = 0x100; in evergreen_gpu_init()
3215 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3216 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3220 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3221 rdev->config.evergreen.max_pipes = 4; in evergreen_gpu_init()
3222 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()
3223 rdev->config.evergreen.max_simds = 10; in evergreen_gpu_init()
3224 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3225 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3226 rdev->config.evergreen.max_threads = 248; in evergreen_gpu_init()
3227 rdev->config.evergreen.max_gs_threads = 32; in evergreen_gpu_init()
3228 rdev->config.evergreen.max_stack_entries = 512; in evergreen_gpu_init()
3229 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3230 rdev->config.evergreen.sx_max_export_size = 256; in evergreen_gpu_init()
3231 rdev->config.evergreen.sx_max_export_pos_size = 64; in evergreen_gpu_init()
3232 rdev->config.evergreen.sx_max_export_smx_size = 192; in evergreen_gpu_init()
3233 rdev->config.evergreen.max_hw_contexts = 8; in evergreen_gpu_init()
3234 rdev->config.evergreen.sq_num_cf_insts = 2; in evergreen_gpu_init()
3236 rdev->config.evergreen.sc_prim_fifo_size = 0x100; in evergreen_gpu_init()
3237 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3238 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3242 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3243 rdev->config.evergreen.max_pipes = 4; in evergreen_gpu_init()
3244 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()
3245 rdev->config.evergreen.max_simds = 5; in evergreen_gpu_init()
3246 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3247 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3248 rdev->config.evergreen.max_threads = 248; in evergreen_gpu_init()
3249 rdev->config.evergreen.max_gs_threads = 32; in evergreen_gpu_init()
3250 rdev->config.evergreen.max_stack_entries = 256; in evergreen_gpu_init()
3251 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3252 rdev->config.evergreen.sx_max_export_size = 256; in evergreen_gpu_init()
3253 rdev->config.evergreen.sx_max_export_pos_size = 64; in evergreen_gpu_init()
3254 rdev->config.evergreen.sx_max_export_smx_size = 192; in evergreen_gpu_init()
3255 rdev->config.evergreen.max_hw_contexts = 8; in evergreen_gpu_init()
3256 rdev->config.evergreen.sq_num_cf_insts = 2; in evergreen_gpu_init()
3258 rdev->config.evergreen.sc_prim_fifo_size = 0x100; in evergreen_gpu_init()
3259 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3260 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3265 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3266 rdev->config.evergreen.max_pipes = 2; in evergreen_gpu_init()
3267 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()
3268 rdev->config.evergreen.max_simds = 2; in evergreen_gpu_init()
3269 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3270 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3271 rdev->config.evergreen.max_threads = 192; in evergreen_gpu_init()
3272 rdev->config.evergreen.max_gs_threads = 16; in evergreen_gpu_init()
3273 rdev->config.evergreen.max_stack_entries = 256; in evergreen_gpu_init()
3274 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3275 rdev->config.evergreen.sx_max_export_size = 128; in evergreen_gpu_init()
3276 rdev->config.evergreen.sx_max_export_pos_size = 32; in evergreen_gpu_init()
3277 rdev->config.evergreen.sx_max_export_smx_size = 96; in evergreen_gpu_init()
3278 rdev->config.evergreen.max_hw_contexts = 4; in evergreen_gpu_init()
3279 rdev->config.evergreen.sq_num_cf_insts = 1; in evergreen_gpu_init()
3281 rdev->config.evergreen.sc_prim_fifo_size = 0x40; in evergreen_gpu_init()
3282 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3283 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3287 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3288 rdev->config.evergreen.max_pipes = 2; in evergreen_gpu_init()
3289 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()
3290 rdev->config.evergreen.max_simds = 2; in evergreen_gpu_init()
3291 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3292 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3293 rdev->config.evergreen.max_threads = 192; in evergreen_gpu_init()
3294 rdev->config.evergreen.max_gs_threads = 16; in evergreen_gpu_init()
3295 rdev->config.evergreen.max_stack_entries = 256; in evergreen_gpu_init()
3296 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3297 rdev->config.evergreen.sx_max_export_size = 128; in evergreen_gpu_init()
3298 rdev->config.evergreen.sx_max_export_pos_size = 32; in evergreen_gpu_init()
3299 rdev->config.evergreen.sx_max_export_smx_size = 96; in evergreen_gpu_init()
3300 rdev->config.evergreen.max_hw_contexts = 4; in evergreen_gpu_init()
3301 rdev->config.evergreen.sq_num_cf_insts = 1; in evergreen_gpu_init()
3303 rdev->config.evergreen.sc_prim_fifo_size = 0x40; in evergreen_gpu_init()
3304 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3305 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3309 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3310 rdev->config.evergreen.max_pipes = 4; in evergreen_gpu_init()
3311 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()
3312 if (rdev->pdev->device == 0x9648) in evergreen_gpu_init()
3313 rdev->config.evergreen.max_simds = 3; in evergreen_gpu_init()
3314 else if ((rdev->pdev->device == 0x9647) || in evergreen_gpu_init()
3315 (rdev->pdev->device == 0x964a)) in evergreen_gpu_init()
3316 rdev->config.evergreen.max_simds = 4; in evergreen_gpu_init()
3318 rdev->config.evergreen.max_simds = 5; in evergreen_gpu_init()
3319 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3320 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3321 rdev->config.evergreen.max_threads = 248; in evergreen_gpu_init()
3322 rdev->config.evergreen.max_gs_threads = 32; in evergreen_gpu_init()
3323 rdev->config.evergreen.max_stack_entries = 256; in evergreen_gpu_init()
3324 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3325 rdev->config.evergreen.sx_max_export_size = 256; in evergreen_gpu_init()
3326 rdev->config.evergreen.sx_max_export_pos_size = 64; in evergreen_gpu_init()
3327 rdev->config.evergreen.sx_max_export_smx_size = 192; in evergreen_gpu_init()
3328 rdev->config.evergreen.max_hw_contexts = 8; in evergreen_gpu_init()
3329 rdev->config.evergreen.sq_num_cf_insts = 2; in evergreen_gpu_init()
3331 rdev->config.evergreen.sc_prim_fifo_size = 0x40; in evergreen_gpu_init()
3332 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3333 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3337 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3338 rdev->config.evergreen.max_pipes = 4; in evergreen_gpu_init()
3339 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()
3340 rdev->config.evergreen.max_simds = 2; in evergreen_gpu_init()
3341 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3342 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3343 rdev->config.evergreen.max_threads = 248; in evergreen_gpu_init()
3344 rdev->config.evergreen.max_gs_threads = 32; in evergreen_gpu_init()
3345 rdev->config.evergreen.max_stack_entries = 512; in evergreen_gpu_init()
3346 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3347 rdev->config.evergreen.sx_max_export_size = 256; in evergreen_gpu_init()
3348 rdev->config.evergreen.sx_max_export_pos_size = 64; in evergreen_gpu_init()
3349 rdev->config.evergreen.sx_max_export_smx_size = 192; in evergreen_gpu_init()
3350 rdev->config.evergreen.max_hw_contexts = 4; in evergreen_gpu_init()
3351 rdev->config.evergreen.sq_num_cf_insts = 2; in evergreen_gpu_init()
3353 rdev->config.evergreen.sc_prim_fifo_size = 0x40; in evergreen_gpu_init()
3354 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3355 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3359 rdev->config.evergreen.num_ses = 2; in evergreen_gpu_init()
3360 rdev->config.evergreen.max_pipes = 4; in evergreen_gpu_init()
3361 rdev->config.evergreen.max_tile_pipes = 8; in evergreen_gpu_init()
3362 rdev->config.evergreen.max_simds = 7; in evergreen_gpu_init()
3363 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3364 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3365 rdev->config.evergreen.max_threads = 248; in evergreen_gpu_init()
3366 rdev->config.evergreen.max_gs_threads = 32; in evergreen_gpu_init()
3367 rdev->config.evergreen.max_stack_entries = 512; in evergreen_gpu_init()
3368 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3369 rdev->config.evergreen.sx_max_export_size = 256; in evergreen_gpu_init()
3370 rdev->config.evergreen.sx_max_export_pos_size = 64; in evergreen_gpu_init()
3371 rdev->config.evergreen.sx_max_export_smx_size = 192; in evergreen_gpu_init()
3372 rdev->config.evergreen.max_hw_contexts = 8; in evergreen_gpu_init()
3373 rdev->config.evergreen.sq_num_cf_insts = 2; in evergreen_gpu_init()
3375 rdev->config.evergreen.sc_prim_fifo_size = 0x100; in evergreen_gpu_init()
3376 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3377 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3381 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3382 rdev->config.evergreen.max_pipes = 4; in evergreen_gpu_init()
3383 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()
3384 rdev->config.evergreen.max_simds = 6; in evergreen_gpu_init()
3385 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3386 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3387 rdev->config.evergreen.max_threads = 248; in evergreen_gpu_init()
3388 rdev->config.evergreen.max_gs_threads = 32; in evergreen_gpu_init()
3389 rdev->config.evergreen.max_stack_entries = 256; in evergreen_gpu_init()
3390 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3391 rdev->config.evergreen.sx_max_export_size = 256; in evergreen_gpu_init()
3392 rdev->config.evergreen.sx_max_export_pos_size = 64; in evergreen_gpu_init()
3393 rdev->config.evergreen.sx_max_export_smx_size = 192; in evergreen_gpu_init()
3394 rdev->config.evergreen.max_hw_contexts = 8; in evergreen_gpu_init()
3395 rdev->config.evergreen.sq_num_cf_insts = 2; in evergreen_gpu_init()
3397 rdev->config.evergreen.sc_prim_fifo_size = 0x100; in evergreen_gpu_init()
3398 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3399 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3403 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3404 rdev->config.evergreen.max_pipes = 2; in evergreen_gpu_init()
3405 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()
3406 rdev->config.evergreen.max_simds = 2; in evergreen_gpu_init()
3407 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3408 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3409 rdev->config.evergreen.max_threads = 192; in evergreen_gpu_init()
3410 rdev->config.evergreen.max_gs_threads = 16; in evergreen_gpu_init()
3411 rdev->config.evergreen.max_stack_entries = 256; in evergreen_gpu_init()
3412 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3413 rdev->config.evergreen.sx_max_export_size = 128; in evergreen_gpu_init()
3414 rdev->config.evergreen.sx_max_export_pos_size = 32; in evergreen_gpu_init()
3415 rdev->config.evergreen.sx_max_export_smx_size = 96; in evergreen_gpu_init()
3416 rdev->config.evergreen.max_hw_contexts = 4; in evergreen_gpu_init()
3417 rdev->config.evergreen.sq_num_cf_insts = 1; in evergreen_gpu_init()
3419 rdev->config.evergreen.sc_prim_fifo_size = 0x40; in evergreen_gpu_init()
3420 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3421 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3439 evergreen_fix_pci_max_read_req_size(rdev); in evergreen_gpu_init()
3442 if ((rdev->family == CHIP_PALM) || in evergreen_gpu_init()
3443 (rdev->family == CHIP_SUMO) || in evergreen_gpu_init()
3444 (rdev->family == CHIP_SUMO2)) in evergreen_gpu_init()
3456 rdev->config.evergreen.tile_config = 0; in evergreen_gpu_init()
3457 switch (rdev->config.evergreen.max_tile_pipes) { in evergreen_gpu_init()
3460 rdev->config.evergreen.tile_config |= (0 << 0); in evergreen_gpu_init()
3463 rdev->config.evergreen.tile_config |= (1 << 0); in evergreen_gpu_init()
3466 rdev->config.evergreen.tile_config |= (2 << 0); in evergreen_gpu_init()
3469 rdev->config.evergreen.tile_config |= (3 << 0); in evergreen_gpu_init()
3473 if (rdev->flags & RADEON_IS_IGP) in evergreen_gpu_init()
3474 rdev->config.evergreen.tile_config |= 1 << 4; in evergreen_gpu_init()
3478 rdev->config.evergreen.tile_config |= 0 << 4; in evergreen_gpu_init()
3481 rdev->config.evergreen.tile_config |= 1 << 4; in evergreen_gpu_init()
3485 rdev->config.evergreen.tile_config |= 2 << 4; in evergreen_gpu_init()
3489 rdev->config.evergreen.tile_config |= 0 << 8; in evergreen_gpu_init()
3490 rdev->config.evergreen.tile_config |= in evergreen_gpu_init()
3493 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) { in evergreen_gpu_init()
3503 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) { in evergreen_gpu_init()
3516 for (i = 0; i < rdev->config.evergreen.max_backends; i++) in evergreen_gpu_init()
3520 for (i = 0; i < rdev->config.evergreen.max_backends; i++) in evergreen_gpu_init()
3524 for (i = 0; i < rdev->config.evergreen.num_ses; i++) { in evergreen_gpu_init()
3530 simd_disable_bitmap |= 0xffffffff << rdev->config.evergreen.max_simds; in evergreen_gpu_init()
3534 rdev->config.evergreen.active_simds = hweight32(~tmp); in evergreen_gpu_init()
3547 if ((rdev->config.evergreen.max_backends == 1) && in evergreen_gpu_init()
3548 (rdev->flags & RADEON_IS_IGP)) { in evergreen_gpu_init()
3558 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends, in evergreen_gpu_init()
3586 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets); in evergreen_gpu_init()
3589 if (rdev->family <= CHIP_SUMO2) in evergreen_gpu_init()
3592 …WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) … in evergreen_gpu_init()
3593 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) | in evergreen_gpu_init()
3594 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1))); in evergreen_gpu_init()
3596 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) | in evergreen_gpu_init()
3597 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) | in evergreen_gpu_init()
3598 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size))); in evergreen_gpu_init()
3605 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) | in evergreen_gpu_init()
3622 switch (rdev->family) { in evergreen_gpu_init()
3637 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32); in evergreen_gpu_init()
3638 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32); in evergreen_gpu_init()
3640 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); in evergreen_gpu_init()
3641 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); in evergreen_gpu_init()
3642 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); in evergreen_gpu_init()
3643 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); in evergreen_gpu_init()
3645 switch (rdev->family) { in evergreen_gpu_init()
3658 …sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count)… in evergreen_gpu_init()
3659 …sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count)… in evergreen_gpu_init()
3660 …sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count)… in evergreen_gpu_init()
3661 …sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count… in evergreen_gpu_init()
3662 …sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_coun… in evergreen_gpu_init()
3664 …sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6… in evergreen_gpu_init()
3665 …sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / … in evergreen_gpu_init()
3666 …sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6… in evergreen_gpu_init()
3667 …sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / … in evergreen_gpu_init()
3668 …sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6… in evergreen_gpu_init()
3669 …sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / … in evergreen_gpu_init()
3686 switch (rdev->family) { in evergreen_gpu_init()
3750 int evergreen_mc_init(struct radeon_device *rdev) in evergreen_mc_init() argument
3756 rdev->mc.vram_is_ddr = true; in evergreen_mc_init()
3757 if ((rdev->family == CHIP_PALM) || in evergreen_mc_init()
3758 (rdev->family == CHIP_SUMO) || in evergreen_mc_init()
3759 (rdev->family == CHIP_SUMO2)) in evergreen_mc_init()
3786 rdev->mc.vram_width = numchan * chansize; in evergreen_mc_init()
3788 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in evergreen_mc_init()
3789 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in evergreen_mc_init()
3791 if ((rdev->family == CHIP_PALM) || in evergreen_mc_init()
3792 (rdev->family == CHIP_SUMO) || in evergreen_mc_init()
3793 (rdev->family == CHIP_SUMO2)) { in evergreen_mc_init()
3795 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); in evergreen_mc_init()
3796 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); in evergreen_mc_init()
3799 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; in evergreen_mc_init()
3800 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; in evergreen_mc_init()
3802 rdev->mc.visible_vram_size = rdev->mc.aper_size; in evergreen_mc_init()
3803 r700_vram_gtt_location(rdev, &rdev->mc); in evergreen_mc_init()
3804 radeon_update_bandwidth_info(rdev); in evergreen_mc_init()
3809 void evergreen_print_gpu_status_regs(struct radeon_device *rdev) in evergreen_print_gpu_status_regs() argument
3811 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n", in evergreen_print_gpu_status_regs()
3813 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n", in evergreen_print_gpu_status_regs()
3815 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n", in evergreen_print_gpu_status_regs()
3817 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n", in evergreen_print_gpu_status_regs()
3819 dev_info(rdev->dev, " SRBM_STATUS2 = 0x%08X\n", in evergreen_print_gpu_status_regs()
3821 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", in evergreen_print_gpu_status_regs()
3823 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", in evergreen_print_gpu_status_regs()
3825 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", in evergreen_print_gpu_status_regs()
3827 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", in evergreen_print_gpu_status_regs()
3829 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", in evergreen_print_gpu_status_regs()
3831 if (rdev->family >= CHIP_CAYMAN) { in evergreen_print_gpu_status_regs()
3832 dev_info(rdev->dev, " R_00D834_DMA_STATUS_REG = 0x%08X\n", in evergreen_print_gpu_status_regs()
3837 bool evergreen_is_display_hung(struct radeon_device *rdev) in evergreen_is_display_hung() argument
3843 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_is_display_hung()
3851 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_is_display_hung()
3866 u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev) in evergreen_gpu_check_soft_reset() argument
3918 if (evergreen_is_display_hung(rdev)) in evergreen_gpu_check_soft_reset()
3935 static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) in evergreen_gpu_soft_reset() argument
3944 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); in evergreen_gpu_soft_reset()
3946 evergreen_print_gpu_status_regs(rdev); in evergreen_gpu_soft_reset()
3960 evergreen_mc_stop(rdev, &save); in evergreen_gpu_soft_reset()
3961 if (evergreen_mc_wait_for_idle(rdev)) { in evergreen_gpu_soft_reset()
3962 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in evergreen_gpu_soft_reset()
4007 if (!(rdev->flags & RADEON_IS_IGP)) { in evergreen_gpu_soft_reset()
4015 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in evergreen_gpu_soft_reset()
4029 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in evergreen_gpu_soft_reset()
4043 evergreen_mc_resume(rdev, &save); in evergreen_gpu_soft_reset()
4046 evergreen_print_gpu_status_regs(rdev); in evergreen_gpu_soft_reset()
4049 void evergreen_gpu_pci_config_reset(struct radeon_device *rdev) in evergreen_gpu_pci_config_reset() argument
4054 dev_info(rdev->dev, "GPU pci config reset\n"); in evergreen_gpu_pci_config_reset()
4068 r600_rlc_stop(rdev); in evergreen_gpu_pci_config_reset()
4073 rv770_set_clk_bypass_mode(rdev); in evergreen_gpu_pci_config_reset()
4075 pci_clear_master(rdev->pdev); in evergreen_gpu_pci_config_reset()
4077 evergreen_mc_stop(rdev, &save); in evergreen_gpu_pci_config_reset()
4078 if (evergreen_mc_wait_for_idle(rdev)) { in evergreen_gpu_pci_config_reset()
4079 dev_warn(rdev->dev, "Wait for MC idle timed out !\n"); in evergreen_gpu_pci_config_reset()
4082 radeon_pci_config_reset(rdev); in evergreen_gpu_pci_config_reset()
4084 for (i = 0; i < rdev->usec_timeout; i++) { in evergreen_gpu_pci_config_reset()
4091 int evergreen_asic_reset(struct radeon_device *rdev) in evergreen_asic_reset() argument
4095 reset_mask = evergreen_gpu_check_soft_reset(rdev); in evergreen_asic_reset()
4098 r600_set_bios_scratch_engine_hung(rdev, true); in evergreen_asic_reset()
4101 evergreen_gpu_soft_reset(rdev, reset_mask); in evergreen_asic_reset()
4103 reset_mask = evergreen_gpu_check_soft_reset(rdev); in evergreen_asic_reset()
4107 evergreen_gpu_pci_config_reset(rdev); in evergreen_asic_reset()
4109 reset_mask = evergreen_gpu_check_soft_reset(rdev); in evergreen_asic_reset()
4112 r600_set_bios_scratch_engine_hung(rdev, false); in evergreen_asic_reset()
4126 bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) in evergreen_gfx_is_lockup() argument
4128 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev); in evergreen_gfx_is_lockup()
4133 radeon_ring_lockup_update(rdev, ring); in evergreen_gfx_is_lockup()
4136 return radeon_ring_test_lockup(rdev, ring); in evergreen_gfx_is_lockup()
4145 void sumo_rlc_fini(struct radeon_device *rdev) in sumo_rlc_fini() argument
4150 if (rdev->rlc.save_restore_obj) { in sumo_rlc_fini()
4151 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); in sumo_rlc_fini()
4153 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r); in sumo_rlc_fini()
4154 radeon_bo_unpin(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4155 radeon_bo_unreserve(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4157 radeon_bo_unref(&rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4158 rdev->rlc.save_restore_obj = NULL; in sumo_rlc_fini()
4162 if (rdev->rlc.clear_state_obj) { in sumo_rlc_fini()
4163 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); in sumo_rlc_fini()
4165 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r); in sumo_rlc_fini()
4166 radeon_bo_unpin(rdev->rlc.clear_state_obj); in sumo_rlc_fini()
4167 radeon_bo_unreserve(rdev->rlc.clear_state_obj); in sumo_rlc_fini()
4169 radeon_bo_unref(&rdev->rlc.clear_state_obj); in sumo_rlc_fini()
4170 rdev->rlc.clear_state_obj = NULL; in sumo_rlc_fini()
4174 if (rdev->rlc.cp_table_obj) { in sumo_rlc_fini()
4175 r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false); in sumo_rlc_fini()
4177 dev_warn(rdev->dev, "(%d) reserve RLC cp table bo failed\n", r); in sumo_rlc_fini()
4178 radeon_bo_unpin(rdev->rlc.cp_table_obj); in sumo_rlc_fini()
4179 radeon_bo_unreserve(rdev->rlc.cp_table_obj); in sumo_rlc_fini()
4181 radeon_bo_unref(&rdev->rlc.cp_table_obj); in sumo_rlc_fini()
4182 rdev->rlc.cp_table_obj = NULL; in sumo_rlc_fini()
4188 int sumo_rlc_init(struct radeon_device *rdev) in sumo_rlc_init() argument
4198 src_ptr = rdev->rlc.reg_list; in sumo_rlc_init()
4199 dws = rdev->rlc.reg_list_size; in sumo_rlc_init()
4200 if (rdev->family >= CHIP_BONAIRE) { in sumo_rlc_init()
4203 cs_data = rdev->rlc.cs_data; in sumo_rlc_init()
4207 if (rdev->rlc.save_restore_obj == NULL) { in sumo_rlc_init()
4208 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true, in sumo_rlc_init()
4210 NULL, &rdev->rlc.save_restore_obj); in sumo_rlc_init()
4212 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r); in sumo_rlc_init()
4217 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); in sumo_rlc_init()
4219 sumo_rlc_fini(rdev); in sumo_rlc_init()
4222 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM, in sumo_rlc_init()
4223 &rdev->rlc.save_restore_gpu_addr); in sumo_rlc_init()
4225 radeon_bo_unreserve(rdev->rlc.save_restore_obj); in sumo_rlc_init()
4226 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r); in sumo_rlc_init()
4227 sumo_rlc_fini(rdev); in sumo_rlc_init()
4231 r = radeon_bo_kmap(rdev->rlc.save_restore_obj, (void **)&rdev->rlc.sr_ptr); in sumo_rlc_init()
4233 dev_warn(rdev->dev, "(%d) map RLC sr bo failed\n", r); in sumo_rlc_init()
4234 sumo_rlc_fini(rdev); in sumo_rlc_init()
4238 dst_ptr = rdev->rlc.sr_ptr; in sumo_rlc_init()
4239 if (rdev->family >= CHIP_TAHITI) { in sumo_rlc_init()
4241 for (i = 0; i < rdev->rlc.reg_list_size; i++) in sumo_rlc_init()
4261 radeon_bo_kunmap(rdev->rlc.save_restore_obj); in sumo_rlc_init()
4262 radeon_bo_unreserve(rdev->rlc.save_restore_obj); in sumo_rlc_init()
4267 if (rdev->family >= CHIP_BONAIRE) { in sumo_rlc_init()
4268 rdev->rlc.clear_state_size = dws = cik_get_csb_size(rdev); in sumo_rlc_init()
4269 } else if (rdev->family >= CHIP_TAHITI) { in sumo_rlc_init()
4270 rdev->rlc.clear_state_size = si_get_csb_size(rdev); in sumo_rlc_init()
4271 dws = rdev->rlc.clear_state_size + (256 / 4); in sumo_rlc_init()
4283 rdev->rlc.clear_state_size = dws; in sumo_rlc_init()
4286 if (rdev->rlc.clear_state_obj == NULL) { in sumo_rlc_init()
4287 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true, in sumo_rlc_init()
4289 NULL, &rdev->rlc.clear_state_obj); in sumo_rlc_init()
4291 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r); in sumo_rlc_init()
4292 sumo_rlc_fini(rdev); in sumo_rlc_init()
4296 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); in sumo_rlc_init()
4298 sumo_rlc_fini(rdev); in sumo_rlc_init()
4301 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM, in sumo_rlc_init()
4302 &rdev->rlc.clear_state_gpu_addr); in sumo_rlc_init()
4304 radeon_bo_unreserve(rdev->rlc.clear_state_obj); in sumo_rlc_init()
4305 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r); in sumo_rlc_init()
4306 sumo_rlc_fini(rdev); in sumo_rlc_init()
4310 r = radeon_bo_kmap(rdev->rlc.clear_state_obj, (void **)&rdev->rlc.cs_ptr); in sumo_rlc_init()
4312 dev_warn(rdev->dev, "(%d) map RLC c bo failed\n", r); in sumo_rlc_init()
4313 sumo_rlc_fini(rdev); in sumo_rlc_init()
4317 dst_ptr = rdev->rlc.cs_ptr; in sumo_rlc_init()
4318 if (rdev->family >= CHIP_BONAIRE) { in sumo_rlc_init()
4319 cik_get_csb_buffer(rdev, dst_ptr); in sumo_rlc_init()
4320 } else if (rdev->family >= CHIP_TAHITI) { in sumo_rlc_init()
4321 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256; in sumo_rlc_init()
4324 dst_ptr[2] = cpu_to_le32(rdev->rlc.clear_state_size); in sumo_rlc_init()
4325 si_get_csb_buffer(rdev, &dst_ptr[(256/4)]); in sumo_rlc_init()
4328 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4); in sumo_rlc_init()
4357 radeon_bo_kunmap(rdev->rlc.clear_state_obj); in sumo_rlc_init()
4358 radeon_bo_unreserve(rdev->rlc.clear_state_obj); in sumo_rlc_init()
4361 if (rdev->rlc.cp_table_size) { in sumo_rlc_init()
4362 if (rdev->rlc.cp_table_obj == NULL) { in sumo_rlc_init()
4363 r = radeon_bo_create(rdev, rdev->rlc.cp_table_size, in sumo_rlc_init()
4366 NULL, &rdev->rlc.cp_table_obj); in sumo_rlc_init()
4368 dev_warn(rdev->dev, "(%d) create RLC cp table bo failed\n", r); in sumo_rlc_init()
4369 sumo_rlc_fini(rdev); in sumo_rlc_init()
4374 r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false); in sumo_rlc_init()
4376 dev_warn(rdev->dev, "(%d) reserve RLC cp table bo failed\n", r); in sumo_rlc_init()
4377 sumo_rlc_fini(rdev); in sumo_rlc_init()
4380 r = radeon_bo_pin(rdev->rlc.cp_table_obj, RADEON_GEM_DOMAIN_VRAM, in sumo_rlc_init()
4381 &rdev->rlc.cp_table_gpu_addr); in sumo_rlc_init()
4383 radeon_bo_unreserve(rdev->rlc.cp_table_obj); in sumo_rlc_init()
4384 dev_warn(rdev->dev, "(%d) pin RLC cp_table bo failed\n", r); in sumo_rlc_init()
4385 sumo_rlc_fini(rdev); in sumo_rlc_init()
4388 r = radeon_bo_kmap(rdev->rlc.cp_table_obj, (void **)&rdev->rlc.cp_table_ptr); in sumo_rlc_init()
4390 dev_warn(rdev->dev, "(%d) map RLC cp table bo failed\n", r); in sumo_rlc_init()
4391 sumo_rlc_fini(rdev); in sumo_rlc_init()
4395 cik_init_cp_pg_table(rdev); in sumo_rlc_init()
4397 radeon_bo_kunmap(rdev->rlc.cp_table_obj); in sumo_rlc_init()
4398 radeon_bo_unreserve(rdev->rlc.cp_table_obj); in sumo_rlc_init()
4405 static void evergreen_rlc_start(struct radeon_device *rdev) in evergreen_rlc_start() argument
4409 if (rdev->flags & RADEON_IS_IGP) { in evergreen_rlc_start()
4416 int evergreen_rlc_resume(struct radeon_device *rdev) in evergreen_rlc_resume() argument
4421 if (!rdev->rlc_fw) in evergreen_rlc_resume()
4424 r600_rlc_stop(rdev); in evergreen_rlc_resume()
4428 if (rdev->flags & RADEON_IS_IGP) { in evergreen_rlc_resume()
4429 if (rdev->family == CHIP_ARUBA) { in evergreen_rlc_resume()
4431 3 | (3 << (16 * rdev->config.cayman.max_shader_engines)); in evergreen_rlc_resume()
4434 tmp |= 0xffffffff << rdev->config.cayman.max_simds_per_se; in evergreen_rlc_resume()
4436 if (tmp == rdev->config.cayman.max_simds_per_se) { in evergreen_rlc_resume()
4447 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in evergreen_rlc_resume()
4448 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in evergreen_rlc_resume()
4459 fw_data = (const __be32 *)rdev->rlc_fw->data; in evergreen_rlc_resume()
4460 if (rdev->family >= CHIP_ARUBA) { in evergreen_rlc_resume()
4465 } else if (rdev->family >= CHIP_CAYMAN) { in evergreen_rlc_resume()
4478 evergreen_rlc_start(rdev); in evergreen_rlc_resume()
4485 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc) in evergreen_get_vblank_counter() argument
4487 if (crtc >= rdev->num_crtc) in evergreen_get_vblank_counter()
4493 void evergreen_disable_interrupt_state(struct radeon_device *rdev) in evergreen_disable_interrupt_state() argument
4497 if (rdev->family >= CHIP_CAYMAN) { in evergreen_disable_interrupt_state()
4498 cayman_cp_int_cntl_setup(rdev, 0, in evergreen_disable_interrupt_state()
4500 cayman_cp_int_cntl_setup(rdev, 1, 0); in evergreen_disable_interrupt_state()
4501 cayman_cp_int_cntl_setup(rdev, 2, 0); in evergreen_disable_interrupt_state()
4512 if (rdev->num_crtc >= 4) { in evergreen_disable_interrupt_state()
4516 if (rdev->num_crtc >= 6) { in evergreen_disable_interrupt_state()
4523 if (rdev->num_crtc >= 4) { in evergreen_disable_interrupt_state()
4527 if (rdev->num_crtc >= 6) { in evergreen_disable_interrupt_state()
4533 if (!ASIC_IS_DCE5(rdev)) in evergreen_disable_interrupt_state()
4552 int evergreen_irq_set(struct radeon_device *rdev) in evergreen_irq_set() argument
4563 if (!rdev->irq.installed) { in evergreen_irq_set()
4568 if (!rdev->ih.enabled) { in evergreen_irq_set()
4569 r600_disable_interrupts(rdev); in evergreen_irq_set()
4571 evergreen_disable_interrupt_state(rdev); in evergreen_irq_set()
4581 if (rdev->family == CHIP_ARUBA) in evergreen_irq_set()
4597 if (rdev->family >= CHIP_CAYMAN) { in evergreen_irq_set()
4599 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in evergreen_irq_set()
4603 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) { in evergreen_irq_set()
4607 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) { in evergreen_irq_set()
4612 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in evergreen_irq_set()
4619 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { in evergreen_irq_set()
4624 if (rdev->family >= CHIP_CAYMAN) { in evergreen_irq_set()
4626 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) { in evergreen_irq_set()
4632 if (rdev->irq.dpm_thermal) { in evergreen_irq_set()
4637 if (rdev->irq.crtc_vblank_int[0] || in evergreen_irq_set()
4638 atomic_read(&rdev->irq.pflip[0])) { in evergreen_irq_set()
4642 if (rdev->irq.crtc_vblank_int[1] || in evergreen_irq_set()
4643 atomic_read(&rdev->irq.pflip[1])) { in evergreen_irq_set()
4647 if (rdev->irq.crtc_vblank_int[2] || in evergreen_irq_set()
4648 atomic_read(&rdev->irq.pflip[2])) { in evergreen_irq_set()
4652 if (rdev->irq.crtc_vblank_int[3] || in evergreen_irq_set()
4653 atomic_read(&rdev->irq.pflip[3])) { in evergreen_irq_set()
4657 if (rdev->irq.crtc_vblank_int[4] || in evergreen_irq_set()
4658 atomic_read(&rdev->irq.pflip[4])) { in evergreen_irq_set()
4662 if (rdev->irq.crtc_vblank_int[5] || in evergreen_irq_set()
4663 atomic_read(&rdev->irq.pflip[5])) { in evergreen_irq_set()
4667 if (rdev->irq.hpd[0]) { in evergreen_irq_set()
4671 if (rdev->irq.hpd[1]) { in evergreen_irq_set()
4675 if (rdev->irq.hpd[2]) { in evergreen_irq_set()
4679 if (rdev->irq.hpd[3]) { in evergreen_irq_set()
4683 if (rdev->irq.hpd[4]) { in evergreen_irq_set()
4687 if (rdev->irq.hpd[5]) { in evergreen_irq_set()
4691 if (rdev->irq.afmt[0]) { in evergreen_irq_set()
4695 if (rdev->irq.afmt[1]) { in evergreen_irq_set()
4699 if (rdev->irq.afmt[2]) { in evergreen_irq_set()
4703 if (rdev->irq.afmt[3]) { in evergreen_irq_set()
4707 if (rdev->irq.afmt[4]) { in evergreen_irq_set()
4711 if (rdev->irq.afmt[5]) { in evergreen_irq_set()
4716 if (rdev->family >= CHIP_CAYMAN) { in evergreen_irq_set()
4717 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl); in evergreen_irq_set()
4718 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1); in evergreen_irq_set()
4719 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2); in evergreen_irq_set()
4725 if (rdev->family >= CHIP_CAYMAN) in evergreen_irq_set()
4732 if (rdev->num_crtc >= 4) { in evergreen_irq_set()
4736 if (rdev->num_crtc >= 6) { in evergreen_irq_set()
4745 if (rdev->num_crtc >= 4) { in evergreen_irq_set()
4751 if (rdev->num_crtc >= 6) { in evergreen_irq_set()
4764 if (rdev->family == CHIP_ARUBA) in evergreen_irq_set()
4782 static void evergreen_irq_ack(struct radeon_device *rdev) in evergreen_irq_ack() argument
4786 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); in evergreen_irq_ack()
4787 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); in evergreen_irq_ack()
4788 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); in evergreen_irq_ack()
4789 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); in evergreen_irq_ack()
4790 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); in evergreen_irq_ack()
4791 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); in evergreen_irq_ack()
4792 …rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSE… in evergreen_irq_ack()
4793 …rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSE… in evergreen_irq_ack()
4794 if (rdev->num_crtc >= 4) { in evergreen_irq_ack()
4795 …rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSE… in evergreen_irq_ack()
4796 …rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSE… in evergreen_irq_ack()
4798 if (rdev->num_crtc >= 6) { in evergreen_irq_ack()
4799 …rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSE… in evergreen_irq_ack()
4800 …rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSE… in evergreen_irq_ack()
4803 rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); in evergreen_irq_ack()
4804 rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); in evergreen_irq_ack()
4805 rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); in evergreen_irq_ack()
4806 rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); in evergreen_irq_ack()
4807 rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); in evergreen_irq_ack()
4808 rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); in evergreen_irq_ack()
4810 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) in evergreen_irq_ack()
4812 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) in evergreen_irq_ack()
4814 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) in evergreen_irq_ack()
4816 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) in evergreen_irq_ack()
4818 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) in evergreen_irq_ack()
4820 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) in evergreen_irq_ack()
4823 if (rdev->num_crtc >= 4) { in evergreen_irq_ack()
4824 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED) in evergreen_irq_ack()
4826 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED) in evergreen_irq_ack()
4828 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) in evergreen_irq_ack()
4830 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) in evergreen_irq_ack()
4832 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) in evergreen_irq_ack()
4834 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) in evergreen_irq_ack()
4838 if (rdev->num_crtc >= 6) { in evergreen_irq_ack()
4839 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED) in evergreen_irq_ack()
4841 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED) in evergreen_irq_ack()
4843 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) in evergreen_irq_ack()
4845 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) in evergreen_irq_ack()
4847 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) in evergreen_irq_ack()
4849 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) in evergreen_irq_ack()
4853 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { in evergreen_irq_ack()
4858 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { in evergreen_irq_ack()
4863 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { in evergreen_irq_ack()
4868 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { in evergreen_irq_ack()
4873 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { in evergreen_irq_ack()
4878 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { in evergreen_irq_ack()
4884 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT) { in evergreen_irq_ack()
4889 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT) { in evergreen_irq_ack()
4894 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) { in evergreen_irq_ack()
4899 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) { in evergreen_irq_ack()
4904 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) { in evergreen_irq_ack()
4909 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) { in evergreen_irq_ack()
4915 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) { in evergreen_irq_ack()
4920 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) { in evergreen_irq_ack()
4925 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) { in evergreen_irq_ack()
4930 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) { in evergreen_irq_ack()
4935 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) { in evergreen_irq_ack()
4940 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) { in evergreen_irq_ack()
4947 static void evergreen_irq_disable(struct radeon_device *rdev) in evergreen_irq_disable() argument
4949 r600_disable_interrupts(rdev); in evergreen_irq_disable()
4952 evergreen_irq_ack(rdev); in evergreen_irq_disable()
4953 evergreen_disable_interrupt_state(rdev); in evergreen_irq_disable()
4956 void evergreen_irq_suspend(struct radeon_device *rdev) in evergreen_irq_suspend() argument
4958 evergreen_irq_disable(rdev); in evergreen_irq_suspend()
4959 r600_rlc_stop(rdev); in evergreen_irq_suspend()
4962 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev) in evergreen_get_ih_wptr() argument
4966 if (rdev->wb.enabled) in evergreen_get_ih_wptr()
4967 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); in evergreen_get_ih_wptr()
4977 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", in evergreen_get_ih_wptr()
4978 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); in evergreen_get_ih_wptr()
4979 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; in evergreen_get_ih_wptr()
4984 return (wptr & rdev->ih.ptr_mask); in evergreen_get_ih_wptr()
4987 int evergreen_irq_process(struct radeon_device *rdev) in evergreen_irq_process() argument
4999 if (!rdev->ih.enabled || rdev->shutdown) in evergreen_irq_process()
5002 wptr = evergreen_get_ih_wptr(rdev); in evergreen_irq_process()
5006 if (atomic_xchg(&rdev->ih.lock, 1)) in evergreen_irq_process()
5009 rptr = rdev->ih.rptr; in evergreen_irq_process()
5016 evergreen_irq_ack(rdev); in evergreen_irq_process()
5021 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; in evergreen_irq_process()
5022 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; in evergreen_irq_process()
5028 if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)) in evergreen_irq_process()
5031 if (rdev->irq.crtc_vblank_int[0]) { in evergreen_irq_process()
5032 drm_handle_vblank(rdev->ddev, 0); in evergreen_irq_process()
5033 rdev->pm.vblank_sync = true; in evergreen_irq_process()
5034 wake_up(&rdev->irq.vblank_queue); in evergreen_irq_process()
5036 if (atomic_read(&rdev->irq.pflip[0])) in evergreen_irq_process()
5037 radeon_crtc_handle_vblank(rdev, 0); in evergreen_irq_process()
5038 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; in evergreen_irq_process()
5043 if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)) in evergreen_irq_process()
5046 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; in evergreen_irq_process()
5058 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)) in evergreen_irq_process()
5061 if (rdev->irq.crtc_vblank_int[1]) { in evergreen_irq_process()
5062 drm_handle_vblank(rdev->ddev, 1); in evergreen_irq_process()
5063 rdev->pm.vblank_sync = true; in evergreen_irq_process()
5064 wake_up(&rdev->irq.vblank_queue); in evergreen_irq_process()
5066 if (atomic_read(&rdev->irq.pflip[1])) in evergreen_irq_process()
5067 radeon_crtc_handle_vblank(rdev, 1); in evergreen_irq_process()
5068 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; in evergreen_irq_process()
5073 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)) in evergreen_irq_process()
5076 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; in evergreen_irq_process()
5088 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)) in evergreen_irq_process()
5091 if (rdev->irq.crtc_vblank_int[2]) { in evergreen_irq_process()
5092 drm_handle_vblank(rdev->ddev, 2); in evergreen_irq_process()
5093 rdev->pm.vblank_sync = true; in evergreen_irq_process()
5094 wake_up(&rdev->irq.vblank_queue); in evergreen_irq_process()
5096 if (atomic_read(&rdev->irq.pflip[2])) in evergreen_irq_process()
5097 radeon_crtc_handle_vblank(rdev, 2); in evergreen_irq_process()
5098 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; in evergreen_irq_process()
5103 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)) in evergreen_irq_process()
5106 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; in evergreen_irq_process()
5118 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)) in evergreen_irq_process()
5121 if (rdev->irq.crtc_vblank_int[3]) { in evergreen_irq_process()
5122 drm_handle_vblank(rdev->ddev, 3); in evergreen_irq_process()
5123 rdev->pm.vblank_sync = true; in evergreen_irq_process()
5124 wake_up(&rdev->irq.vblank_queue); in evergreen_irq_process()
5126 if (atomic_read(&rdev->irq.pflip[3])) in evergreen_irq_process()
5127 radeon_crtc_handle_vblank(rdev, 3); in evergreen_irq_process()
5128 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; in evergreen_irq_process()
5133 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)) in evergreen_irq_process()
5136 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; in evergreen_irq_process()
5148 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)) in evergreen_irq_process()
5151 if (rdev->irq.crtc_vblank_int[4]) { in evergreen_irq_process()
5152 drm_handle_vblank(rdev->ddev, 4); in evergreen_irq_process()
5153 rdev->pm.vblank_sync = true; in evergreen_irq_process()
5154 wake_up(&rdev->irq.vblank_queue); in evergreen_irq_process()
5156 if (atomic_read(&rdev->irq.pflip[4])) in evergreen_irq_process()
5157 radeon_crtc_handle_vblank(rdev, 4); in evergreen_irq_process()
5158 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; in evergreen_irq_process()
5163 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)) in evergreen_irq_process()
5166 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; in evergreen_irq_process()
5178 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)) in evergreen_irq_process()
5181 if (rdev->irq.crtc_vblank_int[5]) { in evergreen_irq_process()
5182 drm_handle_vblank(rdev->ddev, 5); in evergreen_irq_process()
5183 rdev->pm.vblank_sync = true; in evergreen_irq_process()
5184 wake_up(&rdev->irq.vblank_queue); in evergreen_irq_process()
5186 if (atomic_read(&rdev->irq.pflip[5])) in evergreen_irq_process()
5187 radeon_crtc_handle_vblank(rdev, 5); in evergreen_irq_process()
5188 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; in evergreen_irq_process()
5193 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)) in evergreen_irq_process()
5196 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; in evergreen_irq_process()
5213 radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1); in evergreen_irq_process()
5218 if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT)) in evergreen_irq_process()
5221 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; in evergreen_irq_process()
5226 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT)) in evergreen_irq_process()
5229 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; in evergreen_irq_process()
5234 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT)) in evergreen_irq_process()
5237 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; in evergreen_irq_process()
5242 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT)) in evergreen_irq_process()
5245 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; in evergreen_irq_process()
5250 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT)) in evergreen_irq_process()
5253 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; in evergreen_irq_process()
5258 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT)) in evergreen_irq_process()
5261 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; in evergreen_irq_process()
5266 if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT)) in evergreen_irq_process()
5269 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_RX_INTERRUPT; in evergreen_irq_process()
5274 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT)) in evergreen_irq_process()
5277 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT; in evergreen_irq_process()
5282 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT)) in evergreen_irq_process()
5285 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT; in evergreen_irq_process()
5290 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT)) in evergreen_irq_process()
5293 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT; in evergreen_irq_process()
5298 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT)) in evergreen_irq_process()
5301 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT; in evergreen_irq_process()
5306 if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT)) in evergreen_irq_process()
5309 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT; in evergreen_irq_process()
5321 if (!(rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG)) in evergreen_irq_process()
5324 rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG; in evergreen_irq_process()
5329 if (!(rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG)) in evergreen_irq_process()
5332 rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG; in evergreen_irq_process()
5337 if (!(rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG)) in evergreen_irq_process()
5340 rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG; in evergreen_irq_process()
5345 if (!(rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG)) in evergreen_irq_process()
5348 rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG; in evergreen_irq_process()
5353 if (!(rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG)) in evergreen_irq_process()
5356 rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG; in evergreen_irq_process()
5361 if (!(rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG)) in evergreen_irq_process()
5364 rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG; in evergreen_irq_process()
5378 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); in evergreen_irq_process()
5388 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data); in evergreen_irq_process()
5389 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", in evergreen_irq_process()
5391 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", in evergreen_irq_process()
5393 cayman_vm_decode_fault(rdev, status, addr); in evergreen_irq_process()
5399 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in evergreen_irq_process()
5403 if (rdev->family >= CHIP_CAYMAN) { in evergreen_irq_process()
5406 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in evergreen_irq_process()
5409 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX); in evergreen_irq_process()
5412 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX); in evergreen_irq_process()
5416 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in evergreen_irq_process()
5420 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); in evergreen_irq_process()
5424 rdev->pm.dpm.thermal.high_to_low = false; in evergreen_irq_process()
5429 rdev->pm.dpm.thermal.high_to_low = true; in evergreen_irq_process()
5436 if (rdev->family >= CHIP_CAYMAN) { in evergreen_irq_process()
5438 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); in evergreen_irq_process()
5448 rptr &= rdev->ih.ptr_mask; in evergreen_irq_process()
5452 schedule_work(&rdev->dp_work); in evergreen_irq_process()
5454 schedule_work(&rdev->hotplug_work); in evergreen_irq_process()
5456 schedule_work(&rdev->audio_work); in evergreen_irq_process()
5457 if (queue_thermal && rdev->pm.dpm_enabled) in evergreen_irq_process()
5458 schedule_work(&rdev->pm.dpm.thermal.work); in evergreen_irq_process()
5459 rdev->ih.rptr = rptr; in evergreen_irq_process()
5460 atomic_set(&rdev->ih.lock, 0); in evergreen_irq_process()
5463 wptr = evergreen_get_ih_wptr(rdev); in evergreen_irq_process()
5470 static int evergreen_startup(struct radeon_device *rdev) in evergreen_startup() argument
5476 evergreen_pcie_gen2_enable(rdev); in evergreen_startup()
5478 evergreen_program_aspm(rdev); in evergreen_startup()
5481 r = r600_vram_scratch_init(rdev); in evergreen_startup()
5485 evergreen_mc_program(rdev); in evergreen_startup()
5487 if (ASIC_IS_DCE5(rdev) && !rdev->pm.dpm_enabled) { in evergreen_startup()
5488 r = ni_mc_load_microcode(rdev); in evergreen_startup()
5495 if (rdev->flags & RADEON_IS_AGP) { in evergreen_startup()
5496 evergreen_agp_enable(rdev); in evergreen_startup()
5498 r = evergreen_pcie_gart_enable(rdev); in evergreen_startup()
5502 evergreen_gpu_init(rdev); in evergreen_startup()
5505 if (rdev->flags & RADEON_IS_IGP) { in evergreen_startup()
5506 rdev->rlc.reg_list = sumo_rlc_save_restore_register_list; in evergreen_startup()
5507 rdev->rlc.reg_list_size = in evergreen_startup()
5509 rdev->rlc.cs_data = evergreen_cs_data; in evergreen_startup()
5510 r = sumo_rlc_init(rdev); in evergreen_startup()
5518 r = radeon_wb_init(rdev); in evergreen_startup()
5522 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in evergreen_startup()
5524 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in evergreen_startup()
5528 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); in evergreen_startup()
5530 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in evergreen_startup()
5534 r = uvd_v2_2_resume(rdev); in evergreen_startup()
5536 r = radeon_fence_driver_start_ring(rdev, in evergreen_startup()
5539 dev_err(rdev->dev, "UVD fences init error (%d).\n", r); in evergreen_startup()
5543 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in evergreen_startup()
5546 if (!rdev->irq.installed) { in evergreen_startup()
5547 r = radeon_irq_kms_init(rdev); in evergreen_startup()
5552 r = r600_irq_init(rdev); in evergreen_startup()
5555 radeon_irq_kms_fini(rdev); in evergreen_startup()
5558 evergreen_irq_set(rdev); in evergreen_startup()
5560 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in evergreen_startup()
5561 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in evergreen_startup()
5566 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in evergreen_startup()
5567 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, in evergreen_startup()
5572 r = evergreen_cp_load_microcode(rdev); in evergreen_startup()
5575 r = evergreen_cp_resume(rdev); in evergreen_startup()
5578 r = r600_dma_resume(rdev); in evergreen_startup()
5582 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in evergreen_startup()
5584 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, in evergreen_startup()
5587 r = uvd_v1_0_init(rdev); in evergreen_startup()
5593 r = radeon_ib_pool_init(rdev); in evergreen_startup()
5595 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in evergreen_startup()
5599 r = radeon_audio_init(rdev); in evergreen_startup()
5608 int evergreen_resume(struct radeon_device *rdev) in evergreen_resume() argument
5615 if (radeon_asic_reset(rdev)) in evergreen_resume()
5616 dev_warn(rdev->dev, "GPU reset failed !\n"); in evergreen_resume()
5622 atom_asic_init(rdev->mode_info.atom_context); in evergreen_resume()
5625 evergreen_init_golden_registers(rdev); in evergreen_resume()
5627 if (rdev->pm.pm_method == PM_METHOD_DPM) in evergreen_resume()
5628 radeon_pm_resume(rdev); in evergreen_resume()
5630 rdev->accel_working = true; in evergreen_resume()
5631 r = evergreen_startup(rdev); in evergreen_resume()
5634 rdev->accel_working = false; in evergreen_resume()
5642 int evergreen_suspend(struct radeon_device *rdev) in evergreen_suspend() argument
5644 radeon_pm_suspend(rdev); in evergreen_suspend()
5645 radeon_audio_fini(rdev); in evergreen_suspend()
5646 uvd_v1_0_fini(rdev); in evergreen_suspend()
5647 radeon_uvd_suspend(rdev); in evergreen_suspend()
5648 r700_cp_stop(rdev); in evergreen_suspend()
5649 r600_dma_stop(rdev); in evergreen_suspend()
5650 evergreen_irq_suspend(rdev); in evergreen_suspend()
5651 radeon_wb_disable(rdev); in evergreen_suspend()
5652 evergreen_pcie_gart_disable(rdev); in evergreen_suspend()
5663 int evergreen_init(struct radeon_device *rdev) in evergreen_init() argument
5668 if (!radeon_get_bios(rdev)) { in evergreen_init()
5669 if (ASIC_IS_AVIVO(rdev)) in evergreen_init()
5673 if (!rdev->is_atom_bios) { in evergreen_init()
5674 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n"); in evergreen_init()
5677 r = radeon_atombios_init(rdev); in evergreen_init()
5683 if (radeon_asic_reset(rdev)) in evergreen_init()
5684 dev_warn(rdev->dev, "GPU reset failed !\n"); in evergreen_init()
5686 if (!radeon_card_posted(rdev)) { in evergreen_init()
5687 if (!rdev->bios) { in evergreen_init()
5688 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); in evergreen_init()
5692 atom_asic_init(rdev->mode_info.atom_context); in evergreen_init()
5695 evergreen_init_golden_registers(rdev); in evergreen_init()
5697 r600_scratch_init(rdev); in evergreen_init()
5699 radeon_surface_init(rdev); in evergreen_init()
5701 radeon_get_clock_info(rdev->ddev); in evergreen_init()
5703 r = radeon_fence_driver_init(rdev); in evergreen_init()
5707 if (rdev->flags & RADEON_IS_AGP) { in evergreen_init()
5708 r = radeon_agp_init(rdev); in evergreen_init()
5710 radeon_agp_disable(rdev); in evergreen_init()
5713 r = evergreen_mc_init(rdev); in evergreen_init()
5717 r = radeon_bo_init(rdev); in evergreen_init()
5721 if (ASIC_IS_DCE5(rdev)) { in evergreen_init()
5722 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { in evergreen_init()
5723 r = ni_init_microcode(rdev); in evergreen_init()
5730 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in evergreen_init()
5731 r = r600_init_microcode(rdev); in evergreen_init()
5740 radeon_pm_init(rdev); in evergreen_init()
5742 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; in evergreen_init()
5743 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); in evergreen_init()
5745 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; in evergreen_init()
5746 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); in evergreen_init()
5748 r = radeon_uvd_init(rdev); in evergreen_init()
5750 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; in evergreen_init()
5751 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], in evergreen_init()
5755 rdev->ih.ring_obj = NULL; in evergreen_init()
5756 r600_ih_ring_init(rdev, 64 * 1024); in evergreen_init()
5758 r = r600_pcie_gart_init(rdev); in evergreen_init()
5762 rdev->accel_working = true; in evergreen_init()
5763 r = evergreen_startup(rdev); in evergreen_init()
5765 dev_err(rdev->dev, "disabling GPU acceleration\n"); in evergreen_init()
5766 r700_cp_fini(rdev); in evergreen_init()
5767 r600_dma_fini(rdev); in evergreen_init()
5768 r600_irq_fini(rdev); in evergreen_init()
5769 if (rdev->flags & RADEON_IS_IGP) in evergreen_init()
5770 sumo_rlc_fini(rdev); in evergreen_init()
5771 radeon_wb_fini(rdev); in evergreen_init()
5772 radeon_ib_pool_fini(rdev); in evergreen_init()
5773 radeon_irq_kms_fini(rdev); in evergreen_init()
5774 evergreen_pcie_gart_fini(rdev); in evergreen_init()
5775 rdev->accel_working = false; in evergreen_init()
5782 if (ASIC_IS_DCE5(rdev)) { in evergreen_init()
5783 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) { in evergreen_init()
5792 void evergreen_fini(struct radeon_device *rdev) in evergreen_fini() argument
5794 radeon_pm_fini(rdev); in evergreen_fini()
5795 radeon_audio_fini(rdev); in evergreen_fini()
5796 r700_cp_fini(rdev); in evergreen_fini()
5797 r600_dma_fini(rdev); in evergreen_fini()
5798 r600_irq_fini(rdev); in evergreen_fini()
5799 if (rdev->flags & RADEON_IS_IGP) in evergreen_fini()
5800 sumo_rlc_fini(rdev); in evergreen_fini()
5801 radeon_wb_fini(rdev); in evergreen_fini()
5802 radeon_ib_pool_fini(rdev); in evergreen_fini()
5803 radeon_irq_kms_fini(rdev); in evergreen_fini()
5804 uvd_v1_0_fini(rdev); in evergreen_fini()
5805 radeon_uvd_fini(rdev); in evergreen_fini()
5806 evergreen_pcie_gart_fini(rdev); in evergreen_fini()
5807 r600_vram_scratch_fini(rdev); in evergreen_fini()
5808 radeon_gem_fini(rdev); in evergreen_fini()
5809 radeon_fence_driver_fini(rdev); in evergreen_fini()
5810 radeon_agp_fini(rdev); in evergreen_fini()
5811 radeon_bo_fini(rdev); in evergreen_fini()
5812 radeon_atombios_fini(rdev); in evergreen_fini()
5813 kfree(rdev->bios); in evergreen_fini()
5814 rdev->bios = NULL; in evergreen_fini()
5817 void evergreen_pcie_gen2_enable(struct radeon_device *rdev) in evergreen_pcie_gen2_enable() argument
5824 if (rdev->flags & RADEON_IS_IGP) in evergreen_pcie_gen2_enable()
5827 if (!(rdev->flags & RADEON_IS_PCIE)) in evergreen_pcie_gen2_enable()
5831 if (ASIC_IS_X2(rdev)) in evergreen_pcie_gen2_enable()
5834 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && in evergreen_pcie_gen2_enable()
5835 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) in evergreen_pcie_gen2_enable()
5880 void evergreen_program_aspm(struct radeon_device *rdev) in evergreen_program_aspm() argument
5895 if (!(rdev->flags & RADEON_IS_PCIE)) in evergreen_program_aspm()
5898 switch (rdev->family) { in evergreen_program_aspm()
5915 if (rdev->flags & RADEON_IS_IGP) in evergreen_program_aspm()
5937 if (rdev->family >= CHIP_BARTS) in evergreen_program_aspm()
5944 if (rdev->family >= CHIP_BARTS) in evergreen_program_aspm()
5974 if (rdev->family >= CHIP_BARTS) { in evergreen_program_aspm()
6006 if (rdev->family >= CHIP_BARTS) { in evergreen_program_aspm()
6023 if (rdev->family < CHIP_BARTS) in evergreen_program_aspm()