2977 	radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));  in evergreen_ring_ib_execute()
2978 	radeon_ring_write(ring, 1);  in evergreen_ring_ib_execute()
2982 		radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));  in evergreen_ring_ib_execute()
2983 		radeon_ring_write(ring, ((ring->rptr_save_reg -   in evergreen_ring_ib_execute()
2985 		radeon_ring_write(ring, next_rptr);  in evergreen_ring_ib_execute()
2988 		radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));  in evergreen_ring_ib_execute()
2989 		radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);  in evergreen_ring_ib_execute()
2990 		radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));  in evergreen_ring_ib_execute()
2991 		radeon_ring_write(ring, next_rptr);  in evergreen_ring_ib_execute()
2992 		radeon_ring_write(ring, 0);  in evergreen_ring_ib_execute()
2995 	radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));  in evergreen_ring_ib_execute()
2996 	radeon_ring_write(ring,  in evergreen_ring_ib_execute()
3001 	radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);  in evergreen_ring_ib_execute()
3002 	radeon_ring_write(ring, ib->length_dw);  in evergreen_ring_ib_execute()
3049 	radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));  in evergreen_cp_start()
3050 	radeon_ring_write(ring, 0x1);  in evergreen_cp_start()
3051 	radeon_ring_write(ring, 0x0);  in evergreen_cp_start()
3052 	radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);  in evergreen_cp_start()
3053 	radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));  in evergreen_cp_start()
3054 	radeon_ring_write(ring, 0);  in evergreen_cp_start()
3055 	radeon_ring_write(ring, 0);  in evergreen_cp_start()
3068 	radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in evergreen_cp_start()
3069 	radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);  in evergreen_cp_start()
3072 		radeon_ring_write(ring, evergreen_default_state[i]);  in evergreen_cp_start()
3074 	radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));  in evergreen_cp_start()
3075 	radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);  in evergreen_cp_start()
3078 	radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));  in evergreen_cp_start()
3079 	radeon_ring_write(ring, 0);  in evergreen_cp_start()
3082 	radeon_ring_write(ring, 0xc0026f00);  in evergreen_cp_start()
3083 	radeon_ring_write(ring, 0x00000000);  in evergreen_cp_start()
3084 	radeon_ring_write(ring, 0x00000000);  in evergreen_cp_start()
3085 	radeon_ring_write(ring, 0x00000000);  in evergreen_cp_start()
3088 	radeon_ring_write(ring, 0xc0036f00);  in evergreen_cp_start()
3089 	radeon_ring_write(ring, 0x00000bc4);  in evergreen_cp_start()
3090 	radeon_ring_write(ring, 0xffffffff);  in evergreen_cp_start()
3091 	radeon_ring_write(ring, 0xffffffff);  in evergreen_cp_start()
3092 	radeon_ring_write(ring, 0xffffffff);  in evergreen_cp_start()
3094 	radeon_ring_write(ring, 0xc0026900);  in evergreen_cp_start()
3095 	radeon_ring_write(ring, 0x00000316);  in evergreen_cp_start()
3096 	radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */  in evergreen_cp_start()
3097 	radeon_ring_write(ring, 0x00000010); /*  */  in evergreen_cp_start()