Lines Matching refs:radeon_ring_write
144 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); in cik_sdma_ring_ib_execute()
145 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in cik_sdma_ring_ib_execute()
146 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); in cik_sdma_ring_ib_execute()
147 radeon_ring_write(ring, 1); /* number of DWs to follow */ in cik_sdma_ring_ib_execute()
148 radeon_ring_write(ring, next_rptr); in cik_sdma_ring_ib_execute()
153 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); in cik_sdma_ring_ib_execute()
154 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); in cik_sdma_ring_ib_execute()
155 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ in cik_sdma_ring_ib_execute()
156 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); in cik_sdma_ring_ib_execute()
157 radeon_ring_write(ring, ib->length_dw); in cik_sdma_ring_ib_execute()
182 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); in cik_sdma_hdp_flush_ring_emit()
183 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE); in cik_sdma_hdp_flush_ring_emit()
184 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ); in cik_sdma_hdp_flush_ring_emit()
185 radeon_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_hdp_flush_ring_emit()
186 radeon_ring_write(ring, ref_and_mask); /* mask */ in cik_sdma_hdp_flush_ring_emit()
187 radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ in cik_sdma_hdp_flush_ring_emit()
207 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); in cik_sdma_fence_ring_emit()
208 radeon_ring_write(ring, lower_32_bits(addr)); in cik_sdma_fence_ring_emit()
209 radeon_ring_write(ring, upper_32_bits(addr)); in cik_sdma_fence_ring_emit()
210 radeon_ring_write(ring, fence->seq); in cik_sdma_fence_ring_emit()
212 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); in cik_sdma_fence_ring_emit()
236 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits)); in cik_sdma_semaphore_ring_emit()
237 radeon_ring_write(ring, addr & 0xfffffff8); in cik_sdma_semaphore_ring_emit()
238 radeon_ring_write(ring, upper_32_bits(addr)); in cik_sdma_semaphore_ring_emit()
611 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0)); in cik_copy_dma()
612 radeon_ring_write(ring, cur_size_in_bytes); in cik_copy_dma()
613 radeon_ring_write(ring, 0); /* src/dst endian swap */ in cik_copy_dma()
614 radeon_ring_write(ring, lower_32_bits(src_offset)); in cik_copy_dma()
615 radeon_ring_write(ring, upper_32_bits(src_offset)); in cik_copy_dma()
616 radeon_ring_write(ring, lower_32_bits(dst_offset)); in cik_copy_dma()
617 radeon_ring_write(ring, upper_32_bits(dst_offset)); in cik_copy_dma()
669 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); in cik_sdma_ring_test()
670 radeon_ring_write(ring, lower_32_bits(gpu_addr)); in cik_sdma_ring_test()
671 radeon_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test()
672 radeon_ring_write(ring, 1); /* number of DWs to follow */ in cik_sdma_ring_test()
673 radeon_ring_write(ring, 0xDEADBEEF); in cik_sdma_ring_test()
948 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); in cik_dma_vm_flush()
950 radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2); in cik_dma_vm_flush()
952 radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2); in cik_dma_vm_flush()
954 radeon_ring_write(ring, pd_addr >> 12); in cik_dma_vm_flush()
957 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); in cik_dma_vm_flush()
958 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); in cik_dma_vm_flush()
959 radeon_ring_write(ring, VMID(vm_id)); in cik_dma_vm_flush()
961 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); in cik_dma_vm_flush()
962 radeon_ring_write(ring, SH_MEM_BASES >> 2); in cik_dma_vm_flush()
963 radeon_ring_write(ring, 0); in cik_dma_vm_flush()
965 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); in cik_dma_vm_flush()
966 radeon_ring_write(ring, SH_MEM_CONFIG >> 2); in cik_dma_vm_flush()
967 radeon_ring_write(ring, 0); in cik_dma_vm_flush()
969 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); in cik_dma_vm_flush()
970 radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2); in cik_dma_vm_flush()
971 radeon_ring_write(ring, 1); in cik_dma_vm_flush()
973 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); in cik_dma_vm_flush()
974 radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2); in cik_dma_vm_flush()
975 radeon_ring_write(ring, 0); in cik_dma_vm_flush()
977 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); in cik_dma_vm_flush()
978 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); in cik_dma_vm_flush()
979 radeon_ring_write(ring, VMID(0)); in cik_dma_vm_flush()
985 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); in cik_dma_vm_flush()
986 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in cik_dma_vm_flush()
987 radeon_ring_write(ring, 1 << vm_id); in cik_dma_vm_flush()
989 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); in cik_dma_vm_flush()
990 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in cik_dma_vm_flush()
991 radeon_ring_write(ring, 0); in cik_dma_vm_flush()
992 radeon_ring_write(ring, 0); /* reference */ in cik_dma_vm_flush()
993 radeon_ring_write(ring, 0); /* mask */ in cik_dma_vm_flush()
994 radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ in cik_dma_vm_flush()