6220 static void cik_update_rlc(struct radeon_device *rdev, u32 rlc)  in cik_update_rlc()  argument
6225 	if (tmp != rlc)  in cik_update_rlc()
6226 		WREG32(RLC_CNTL, rlc);  in cik_update_rlc()
6842 	if (rdev->rlc.cp_table_ptr == NULL)  in cik_init_cp_pg_table()
6846 	dst_ptr = rdev->rlc.cp_table_ptr;  in cik_init_cp_pg_table()
7040 	if (rdev->rlc.cs_data) {  in cik_init_gfx_cgpg()
7042 		WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr));  in cik_init_gfx_cgpg()
7043 		WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr));  in cik_init_gfx_cgpg()
7044 		WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size);  in cik_init_gfx_cgpg()
7050 	if (rdev->rlc.reg_list) {  in cik_init_gfx_cgpg()
7052 		for (i = 0; i < rdev->rlc.reg_list_size; i++)  in cik_init_gfx_cgpg()
7053 			WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.reg_list[i]);  in cik_init_gfx_cgpg()
7061 	WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);  in cik_init_gfx_cgpg()
7062 	WREG32(RLC_CP_TABLE_RESTORE, rdev->rlc.cp_table_gpu_addr >> 8);  in cik_init_gfx_cgpg()
7097 	if (rdev->rlc.cs_data == NULL)  in cik_get_csb_size()
7105 	for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {  in cik_get_csb_size()
7129 	if (rdev->rlc.cs_data == NULL)  in cik_get_csb_buffer()
7141 	for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {  in cik_get_csb_buffer()
8514 			rdev->rlc.reg_list = spectre_rlc_save_restore_register_list;  in cik_startup()
8515 			rdev->rlc.reg_list_size =  in cik_startup()
8518 			rdev->rlc.reg_list = kalindi_rlc_save_restore_register_list;  in cik_startup()
8519 			rdev->rlc.reg_list_size =  in cik_startup()
8523 	rdev->rlc.cs_data = ci_cs_data;  in cik_startup()
8524 	rdev->rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4;  in cik_startup()