Lines Matching refs:ring
3842 int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring) in cik_ring_test() argument
3855 r = radeon_ring_lock(rdev, ring, 3); in cik_ring_test()
3857 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r); in cik_ring_test()
3861 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in cik_ring_test()
3862 radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2)); in cik_ring_test()
3863 radeon_ring_write(ring, 0xDEADBEEF); in cik_ring_test()
3864 radeon_ring_unlock_commit(rdev, ring, false); in cik_ring_test()
3873 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); in cik_ring_test()
3876 ring->idx, scratch, tmp); in cik_ring_test()
3894 struct radeon_ring *ring = &rdev->ring[ridx]; in cik_hdp_flush_cp_ring_emit() local
3897 switch (ring->idx) { in cik_hdp_flush_cp_ring_emit()
3901 switch (ring->me) { in cik_hdp_flush_cp_ring_emit()
3903 ref_and_mask = CP2 << ring->pipe; in cik_hdp_flush_cp_ring_emit()
3906 ref_and_mask = CP6 << ring->pipe; in cik_hdp_flush_cp_ring_emit()
3917 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_hdp_flush_cp_ring_emit()
3918 radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ in cik_hdp_flush_cp_ring_emit()
3921 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ >> 2); in cik_hdp_flush_cp_ring_emit()
3922 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE >> 2); in cik_hdp_flush_cp_ring_emit()
3923 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
3924 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
3925 radeon_ring_write(ring, 0x20); /* poll interval */ in cik_hdp_flush_cp_ring_emit()
3940 struct radeon_ring *ring = &rdev->ring[fence->ring]; in cik_fence_gfx_ring_emit() local
3941 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cik_fence_gfx_ring_emit()
3946 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3947 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | in cik_fence_gfx_ring_emit()
3951 radeon_ring_write(ring, addr & 0xfffffffc); in cik_fence_gfx_ring_emit()
3952 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | in cik_fence_gfx_ring_emit()
3954 radeon_ring_write(ring, fence->seq - 1); in cik_fence_gfx_ring_emit()
3955 radeon_ring_write(ring, 0); in cik_fence_gfx_ring_emit()
3958 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3959 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | in cik_fence_gfx_ring_emit()
3963 radeon_ring_write(ring, addr & 0xfffffffc); in cik_fence_gfx_ring_emit()
3964 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2)); in cik_fence_gfx_ring_emit()
3965 radeon_ring_write(ring, fence->seq); in cik_fence_gfx_ring_emit()
3966 radeon_ring_write(ring, 0); in cik_fence_gfx_ring_emit()
3981 struct radeon_ring *ring = &rdev->ring[fence->ring]; in cik_fence_compute_ring_emit() local
3982 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cik_fence_compute_ring_emit()
3985 radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); in cik_fence_compute_ring_emit()
3986 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | in cik_fence_compute_ring_emit()
3990 radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2)); in cik_fence_compute_ring_emit()
3991 radeon_ring_write(ring, addr & 0xfffffffc); in cik_fence_compute_ring_emit()
3992 radeon_ring_write(ring, upper_32_bits(addr)); in cik_fence_compute_ring_emit()
3993 radeon_ring_write(ring, fence->seq); in cik_fence_compute_ring_emit()
3994 radeon_ring_write(ring, 0); in cik_fence_compute_ring_emit()
4009 struct radeon_ring *ring, in cik_semaphore_ring_emit() argument
4016 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in cik_semaphore_ring_emit()
4017 radeon_ring_write(ring, lower_32_bits(addr)); in cik_semaphore_ring_emit()
4018 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel); in cik_semaphore_ring_emit()
4020 if (emit_wait && ring->idx == RADEON_RING_TYPE_GFX_INDEX) { in cik_semaphore_ring_emit()
4022 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cik_semaphore_ring_emit()
4023 radeon_ring_write(ring, 0x0); in cik_semaphore_ring_emit()
4050 struct radeon_ring *ring = &rdev->ring[ring_index]; in cik_copy_cpdma() local
4059 r = radeon_ring_lock(rdev, ring, num_loops * 7 + 18); in cik_copy_cpdma()
4067 radeon_sync_rings(rdev, &sync, ring->idx); in cik_copy_cpdma()
4077 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); in cik_copy_cpdma()
4078 radeon_ring_write(ring, control); in cik_copy_cpdma()
4079 radeon_ring_write(ring, lower_32_bits(src_offset)); in cik_copy_cpdma()
4080 radeon_ring_write(ring, upper_32_bits(src_offset)); in cik_copy_cpdma()
4081 radeon_ring_write(ring, lower_32_bits(dst_offset)); in cik_copy_cpdma()
4082 radeon_ring_write(ring, upper_32_bits(dst_offset)); in cik_copy_cpdma()
4083 radeon_ring_write(ring, cur_size_in_bytes); in cik_copy_cpdma()
4088 r = radeon_fence_emit(rdev, &fence, ring->idx); in cik_copy_cpdma()
4090 radeon_ring_unlock_undo(rdev, ring); in cik_copy_cpdma()
4095 radeon_ring_unlock_commit(rdev, ring, false); in cik_copy_cpdma()
4118 struct radeon_ring *ring = &rdev->ring[ib->ring]; in cik_ring_ib_execute() local
4119 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0; in cik_ring_ib_execute()
4124 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in cik_ring_ib_execute()
4125 radeon_ring_write(ring, 0); in cik_ring_ib_execute()
4130 if (ring->rptr_save_reg) { in cik_ring_ib_execute()
4131 next_rptr = ring->wptr + 3 + 4; in cik_ring_ib_execute()
4132 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in cik_ring_ib_execute()
4133 radeon_ring_write(ring, ((ring->rptr_save_reg - in cik_ring_ib_execute()
4135 radeon_ring_write(ring, next_rptr); in cik_ring_ib_execute()
4137 next_rptr = ring->wptr + 5 + 4; in cik_ring_ib_execute()
4138 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_ring_ib_execute()
4139 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); in cik_ring_ib_execute()
4140 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in cik_ring_ib_execute()
4141 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); in cik_ring_ib_execute()
4142 radeon_ring_write(ring, next_rptr); in cik_ring_ib_execute()
4150 radeon_ring_write(ring, header); in cik_ring_ib_execute()
4151 radeon_ring_write(ring, in cik_ring_ib_execute()
4156 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in cik_ring_ib_execute()
4157 radeon_ring_write(ring, control); in cik_ring_ib_execute()
4170 int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) in cik_ib_test() argument
4184 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256); in cik_ib_test()
4215 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i); in cik_ib_test()
4265 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cik_cp_gfx_enable()
4367 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cik_cp_gfx_start() local
4377 r = radeon_ring_lock(rdev, ring, cik_default_size + 17); in cik_cp_gfx_start()
4384 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in cik_cp_gfx_start()
4385 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in cik_cp_gfx_start()
4386 radeon_ring_write(ring, 0x8000); in cik_cp_gfx_start()
4387 radeon_ring_write(ring, 0x8000); in cik_cp_gfx_start()
4390 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cik_cp_gfx_start()
4391 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cik_cp_gfx_start()
4393 radeon_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in cik_cp_gfx_start()
4394 radeon_ring_write(ring, 0x80000000); in cik_cp_gfx_start()
4395 radeon_ring_write(ring, 0x80000000); in cik_cp_gfx_start()
4398 radeon_ring_write(ring, cik_default_state[i]); in cik_cp_gfx_start()
4400 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cik_cp_gfx_start()
4401 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in cik_cp_gfx_start()
4404 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cik_cp_gfx_start()
4405 radeon_ring_write(ring, 0); in cik_cp_gfx_start()
4407 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in cik_cp_gfx_start()
4408 radeon_ring_write(ring, 0x00000316); in cik_cp_gfx_start()
4409 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ in cik_cp_gfx_start()
4410 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ in cik_cp_gfx_start()
4412 radeon_ring_unlock_commit(rdev, ring, false); in cik_cp_gfx_start()
4428 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in cik_cp_gfx_fini()
4442 struct radeon_ring *ring; in cik_cp_gfx_resume() local
4462 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cik_cp_gfx_resume()
4463 rb_bufsz = order_base_2(ring->ring_size / 8); in cik_cp_gfx_resume()
4472 ring->wptr = 0; in cik_cp_gfx_resume()
4473 WREG32(CP_RB0_WPTR, ring->wptr); in cik_cp_gfx_resume()
4488 rb_addr = ring->gpu_addr >> 8; in cik_cp_gfx_resume()
4494 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; in cik_cp_gfx_resume()
4495 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in cik_cp_gfx_resume()
4497 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cik_cp_gfx_resume()
4508 struct radeon_ring *ring) in cik_gfx_get_rptr() argument
4513 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cik_gfx_get_rptr()
4521 struct radeon_ring *ring) in cik_gfx_get_wptr() argument
4531 struct radeon_ring *ring) in cik_gfx_set_wptr() argument
4533 WREG32(CP_RB0_WPTR, ring->wptr); in cik_gfx_set_wptr()
4538 struct radeon_ring *ring) in cik_compute_get_rptr() argument
4543 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cik_compute_get_rptr()
4546 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0); in cik_compute_get_rptr()
4556 struct radeon_ring *ring) in cik_compute_get_wptr() argument
4562 wptr = rdev->wb.wb[ring->wptr_offs/4]; in cik_compute_get_wptr()
4565 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0); in cik_compute_get_wptr()
4575 struct radeon_ring *ring) in cik_compute_set_wptr() argument
4578 rdev->wb.wb[ring->wptr_offs/4] = ring->wptr; in cik_compute_set_wptr()
4579 WDOORBELL32(ring->doorbell_index, ring->wptr); in cik_compute_set_wptr()
4583 struct radeon_ring *ring) in cik_compute_stop() argument
4587 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0); in cik_compute_stop()
4625 cik_compute_stop(rdev,&rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]); in cik_cp_compute_enable()
4626 cik_compute_stop(rdev,&rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]); in cik_cp_compute_enable()
4630 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in cik_cp_compute_enable()
4631 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in cik_cp_compute_enable()
4742 if (rdev->ring[idx].mqd_obj) { in cik_cp_compute_fini()
4743 r = radeon_bo_reserve(rdev->ring[idx].mqd_obj, false); in cik_cp_compute_fini()
4747 radeon_bo_unpin(rdev->ring[idx].mqd_obj); in cik_cp_compute_fini()
4748 radeon_bo_unreserve(rdev->ring[idx].mqd_obj); in cik_cp_compute_fini()
4750 radeon_bo_unref(&rdev->ring[idx].mqd_obj); in cik_cp_compute_fini()
4751 rdev->ring[idx].mqd_obj = NULL; in cik_cp_compute_fini()
4955 if (rdev->ring[idx].mqd_obj == NULL) { in cik_cp_compute_resume()
4960 NULL, &rdev->ring[idx].mqd_obj); in cik_cp_compute_resume()
4967 r = radeon_bo_reserve(rdev->ring[idx].mqd_obj, false); in cik_cp_compute_resume()
4972 r = radeon_bo_pin(rdev->ring[idx].mqd_obj, RADEON_GEM_DOMAIN_GTT, in cik_cp_compute_resume()
4979 r = radeon_bo_kmap(rdev->ring[idx].mqd_obj, (void **)&buf); in cik_cp_compute_resume()
4997 cik_srbm_select(rdev, rdev->ring[idx].me, in cik_cp_compute_resume()
4998 rdev->ring[idx].pipe, in cik_cp_compute_resume()
4999 rdev->ring[idx].queue, 0); in cik_cp_compute_resume()
5043 hqd_gpu_addr = rdev->ring[idx].gpu_addr >> 8; in cik_cp_compute_resume()
5055 order_base_2(rdev->ring[idx].ring_size / 8); in cik_cp_compute_resume()
5097 DOORBELL_OFFSET(rdev->ring[idx].doorbell_index); in cik_cp_compute_resume()
5109 rdev->ring[idx].wptr = 0; in cik_cp_compute_resume()
5110 mqd->queue_state.cp_hqd_pq_wptr = rdev->ring[idx].wptr; in cik_cp_compute_resume()
5125 radeon_bo_kunmap(rdev->ring[idx].mqd_obj); in cik_cp_compute_resume()
5126 radeon_bo_unreserve(rdev->ring[idx].mqd_obj); in cik_cp_compute_resume()
5128 rdev->ring[idx].ready = true; in cik_cp_compute_resume()
5129 r = radeon_ring_test(rdev, idx, &rdev->ring[idx]); in cik_cp_compute_resume()
5131 rdev->ring[idx].ready = false; in cik_cp_compute_resume()
5635 bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) in cik_gfx_is_lockup() argument
5642 radeon_ring_lockup_update(rdev, ring); in cik_gfx_is_lockup()
5645 return radeon_ring_test_lockup(rdev, ring); in cik_gfx_is_lockup()
6089 void cik_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, in cik_vm_flush() argument
6092 int usepfp = (ring->idx == RADEON_RING_TYPE_GFX_INDEX); in cik_vm_flush()
6094 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
6095 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
6098 radeon_ring_write(ring, in cik_vm_flush()
6101 radeon_ring_write(ring, in cik_vm_flush()
6104 radeon_ring_write(ring, 0); in cik_vm_flush()
6105 radeon_ring_write(ring, pd_addr >> 12); in cik_vm_flush()
6108 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
6109 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
6111 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); in cik_vm_flush()
6112 radeon_ring_write(ring, 0); in cik_vm_flush()
6113 radeon_ring_write(ring, VMID(vm_id)); in cik_vm_flush()
6115 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); in cik_vm_flush()
6116 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
6118 radeon_ring_write(ring, SH_MEM_BASES >> 2); in cik_vm_flush()
6119 radeon_ring_write(ring, 0); in cik_vm_flush()
6121 radeon_ring_write(ring, 0); /* SH_MEM_BASES */ in cik_vm_flush()
6122 radeon_ring_write(ring, 0); /* SH_MEM_CONFIG */ in cik_vm_flush()
6123 radeon_ring_write(ring, 1); /* SH_MEM_APE1_BASE */ in cik_vm_flush()
6124 radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */ in cik_vm_flush()
6126 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
6127 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
6129 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); in cik_vm_flush()
6130 radeon_ring_write(ring, 0); in cik_vm_flush()
6131 radeon_ring_write(ring, VMID(0)); in cik_vm_flush()
6134 cik_hdp_flush_cp_ring_emit(rdev, ring->idx); in cik_vm_flush()
6137 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
6138 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
6140 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in cik_vm_flush()
6141 radeon_ring_write(ring, 0); in cik_vm_flush()
6142 radeon_ring_write(ring, 1 << vm_id); in cik_vm_flush()
6145 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_vm_flush()
6146 radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ in cik_vm_flush()
6149 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in cik_vm_flush()
6150 radeon_ring_write(ring, 0); in cik_vm_flush()
6151 radeon_ring_write(ring, 0); /* ref */ in cik_vm_flush()
6152 radeon_ring_write(ring, 0); /* mask */ in cik_vm_flush()
6153 radeon_ring_write(ring, 0x20); /* poll interval */ in cik_vm_flush()
6158 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cik_vm_flush()
6159 radeon_ring_write(ring, 0x0); in cik_vm_flush()
7482 struct radeon_ring *ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in cik_irq_set() local
7484 if (ring->me == 1) { in cik_irq_set()
7485 switch (ring->pipe) { in cik_irq_set()
7490 DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe); in cik_irq_set()
7494 DRM_DEBUG("si_irq_set: sw int cp1 invalid me %d\n", ring->me); in cik_irq_set()
7498 struct radeon_ring *ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; in cik_irq_set() local
7500 if (ring->me == 1) { in cik_irq_set()
7501 switch (ring->pipe) { in cik_irq_set()
7506 DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe); in cik_irq_set()
7510 DRM_DEBUG("si_irq_set: sw int cp2 invalid me %d\n", ring->me); in cik_irq_set()
7895 struct radeon_ring *cp1_ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in cik_irq_process()
7896 struct radeon_ring *cp2_ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; in cik_irq_process()
7932 (const void *) &rdev->ih.ring[ring_index]); in cik_irq_process()
7934 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; in cik_irq_process()
7935 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; in cik_irq_process()
7936 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff; in cik_irq_process()
8482 struct radeon_ring *ring; in cik_startup() local
8584 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in cik_startup()
8598 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0; in cik_startup()
8599 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0; in cik_startup()
8626 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cik_startup()
8627 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in cik_startup()
8634 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in cik_startup()
8635 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET, in cik_startup()
8639 ring->me = 1; /* first MEC */ in cik_startup()
8640 ring->pipe = 0; /* first pipe */ in cik_startup()
8641 ring->queue = 0; /* first queue */ in cik_startup()
8642 ring->wptr_offs = CIK_WB_CP1_WPTR_OFFSET; in cik_startup()
8645 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; in cik_startup()
8646 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET, in cik_startup()
8651 ring->me = 1; /* first MEC */ in cik_startup()
8652 ring->pipe = 0; /* first pipe */ in cik_startup()
8653 ring->queue = 1; /* second queue */ in cik_startup()
8654 ring->wptr_offs = CIK_WB_CP2_WPTR_OFFSET; in cik_startup()
8656 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cik_startup()
8657 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, in cik_startup()
8662 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cik_startup()
8663 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, in cik_startup()
8676 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in cik_startup()
8677 if (ring->ring_size) { in cik_startup()
8678 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, in cik_startup()
8688 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; in cik_startup()
8689 if (ring->ring_size) in cik_startup()
8690 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, in cik_startup()
8693 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; in cik_startup()
8694 if (ring->ring_size) in cik_startup()
8695 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, in cik_startup()
8806 struct radeon_ring *ring; in cik_init() local
8879 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cik_init()
8880 ring->ring_obj = NULL; in cik_init()
8881 r600_ring_init(rdev, ring, 1024 * 1024); in cik_init()
8883 ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX]; in cik_init()
8884 ring->ring_obj = NULL; in cik_init()
8885 r600_ring_init(rdev, ring, 1024 * 1024); in cik_init()
8886 r = radeon_doorbell_get(rdev, &ring->doorbell_index); in cik_init()
8890 ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX]; in cik_init()
8891 ring->ring_obj = NULL; in cik_init()
8892 r600_ring_init(rdev, ring, 1024 * 1024); in cik_init()
8893 r = radeon_doorbell_get(rdev, &ring->doorbell_index); in cik_init()
8897 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cik_init()
8898 ring->ring_obj = NULL; in cik_init()
8899 r600_ring_init(rdev, ring, 256 * 1024); in cik_init()
8901 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cik_init()
8902 ring->ring_obj = NULL; in cik_init()
8903 r600_ring_init(rdev, ring, 256 * 1024); in cik_init()
8907 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in cik_init()
8908 ring->ring_obj = NULL; in cik_init()
8909 r600_ring_init(rdev, ring, 4096); in cik_init()
8914 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; in cik_init()
8915 ring->ring_obj = NULL; in cik_init()
8916 r600_ring_init(rdev, ring, 4096); in cik_init()
8918 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; in cik_init()
8919 ring->ring_obj = NULL; in cik_init()
8920 r600_ring_init(rdev, ring, 4096); in cik_init()