Lines Matching refs:radeon_ring_write
3861 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in cik_ring_test()
3862 radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2)); in cik_ring_test()
3863 radeon_ring_write(ring, 0xDEADBEEF); in cik_ring_test()
3917 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_hdp_flush_cp_ring_emit()
3918 radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ in cik_hdp_flush_cp_ring_emit()
3921 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ >> 2); in cik_hdp_flush_cp_ring_emit()
3922 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE >> 2); in cik_hdp_flush_cp_ring_emit()
3923 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
3924 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
3925 radeon_ring_write(ring, 0x20); /* poll interval */ in cik_hdp_flush_cp_ring_emit()
3946 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3947 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | in cik_fence_gfx_ring_emit()
3951 radeon_ring_write(ring, addr & 0xfffffffc); in cik_fence_gfx_ring_emit()
3952 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | in cik_fence_gfx_ring_emit()
3954 radeon_ring_write(ring, fence->seq - 1); in cik_fence_gfx_ring_emit()
3955 radeon_ring_write(ring, 0); in cik_fence_gfx_ring_emit()
3958 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3959 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | in cik_fence_gfx_ring_emit()
3963 radeon_ring_write(ring, addr & 0xfffffffc); in cik_fence_gfx_ring_emit()
3964 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2)); in cik_fence_gfx_ring_emit()
3965 radeon_ring_write(ring, fence->seq); in cik_fence_gfx_ring_emit()
3966 radeon_ring_write(ring, 0); in cik_fence_gfx_ring_emit()
3985 radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); in cik_fence_compute_ring_emit()
3986 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | in cik_fence_compute_ring_emit()
3990 radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2)); in cik_fence_compute_ring_emit()
3991 radeon_ring_write(ring, addr & 0xfffffffc); in cik_fence_compute_ring_emit()
3992 radeon_ring_write(ring, upper_32_bits(addr)); in cik_fence_compute_ring_emit()
3993 radeon_ring_write(ring, fence->seq); in cik_fence_compute_ring_emit()
3994 radeon_ring_write(ring, 0); in cik_fence_compute_ring_emit()
4016 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in cik_semaphore_ring_emit()
4017 radeon_ring_write(ring, lower_32_bits(addr)); in cik_semaphore_ring_emit()
4018 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel); in cik_semaphore_ring_emit()
4022 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cik_semaphore_ring_emit()
4023 radeon_ring_write(ring, 0x0); in cik_semaphore_ring_emit()
4077 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); in cik_copy_cpdma()
4078 radeon_ring_write(ring, control); in cik_copy_cpdma()
4079 radeon_ring_write(ring, lower_32_bits(src_offset)); in cik_copy_cpdma()
4080 radeon_ring_write(ring, upper_32_bits(src_offset)); in cik_copy_cpdma()
4081 radeon_ring_write(ring, lower_32_bits(dst_offset)); in cik_copy_cpdma()
4082 radeon_ring_write(ring, upper_32_bits(dst_offset)); in cik_copy_cpdma()
4083 radeon_ring_write(ring, cur_size_in_bytes); in cik_copy_cpdma()
4124 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in cik_ring_ib_execute()
4125 radeon_ring_write(ring, 0); in cik_ring_ib_execute()
4132 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in cik_ring_ib_execute()
4133 radeon_ring_write(ring, ((ring->rptr_save_reg - in cik_ring_ib_execute()
4135 radeon_ring_write(ring, next_rptr); in cik_ring_ib_execute()
4138 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_ring_ib_execute()
4139 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); in cik_ring_ib_execute()
4140 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in cik_ring_ib_execute()
4141 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); in cik_ring_ib_execute()
4142 radeon_ring_write(ring, next_rptr); in cik_ring_ib_execute()
4150 radeon_ring_write(ring, header); in cik_ring_ib_execute()
4151 radeon_ring_write(ring, in cik_ring_ib_execute()
4156 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in cik_ring_ib_execute()
4157 radeon_ring_write(ring, control); in cik_ring_ib_execute()
4384 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in cik_cp_gfx_start()
4385 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in cik_cp_gfx_start()
4386 radeon_ring_write(ring, 0x8000); in cik_cp_gfx_start()
4387 radeon_ring_write(ring, 0x8000); in cik_cp_gfx_start()
4390 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cik_cp_gfx_start()
4391 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cik_cp_gfx_start()
4393 radeon_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in cik_cp_gfx_start()
4394 radeon_ring_write(ring, 0x80000000); in cik_cp_gfx_start()
4395 radeon_ring_write(ring, 0x80000000); in cik_cp_gfx_start()
4398 radeon_ring_write(ring, cik_default_state[i]); in cik_cp_gfx_start()
4400 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cik_cp_gfx_start()
4401 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in cik_cp_gfx_start()
4404 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cik_cp_gfx_start()
4405 radeon_ring_write(ring, 0); in cik_cp_gfx_start()
4407 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in cik_cp_gfx_start()
4408 radeon_ring_write(ring, 0x00000316); in cik_cp_gfx_start()
4409 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ in cik_cp_gfx_start()
4410 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ in cik_cp_gfx_start()
6094 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
6095 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
6098 radeon_ring_write(ring, in cik_vm_flush()
6101 radeon_ring_write(ring, in cik_vm_flush()
6104 radeon_ring_write(ring, 0); in cik_vm_flush()
6105 radeon_ring_write(ring, pd_addr >> 12); in cik_vm_flush()
6108 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
6109 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
6111 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); in cik_vm_flush()
6112 radeon_ring_write(ring, 0); in cik_vm_flush()
6113 radeon_ring_write(ring, VMID(vm_id)); in cik_vm_flush()
6115 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); in cik_vm_flush()
6116 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
6118 radeon_ring_write(ring, SH_MEM_BASES >> 2); in cik_vm_flush()
6119 radeon_ring_write(ring, 0); in cik_vm_flush()
6121 radeon_ring_write(ring, 0); /* SH_MEM_BASES */ in cik_vm_flush()
6122 radeon_ring_write(ring, 0); /* SH_MEM_CONFIG */ in cik_vm_flush()
6123 radeon_ring_write(ring, 1); /* SH_MEM_APE1_BASE */ in cik_vm_flush()
6124 radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */ in cik_vm_flush()
6126 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
6127 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
6129 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); in cik_vm_flush()
6130 radeon_ring_write(ring, 0); in cik_vm_flush()
6131 radeon_ring_write(ring, VMID(0)); in cik_vm_flush()
6137 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
6138 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
6140 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in cik_vm_flush()
6141 radeon_ring_write(ring, 0); in cik_vm_flush()
6142 radeon_ring_write(ring, 1 << vm_id); in cik_vm_flush()
6145 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_vm_flush()
6146 radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ in cik_vm_flush()
6149 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in cik_vm_flush()
6150 radeon_ring_write(ring, 0); in cik_vm_flush()
6151 radeon_ring_write(ring, 0); /* ref */ in cik_vm_flush()
6152 radeon_ring_write(ring, 0); /* mask */ in cik_vm_flush()
6153 radeon_ring_write(ring, 0x20); /* poll interval */ in cik_vm_flush()
6158 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cik_vm_flush()
6159 radeon_ring_write(ring, 0x0); in cik_vm_flush()