166 	case (SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET):  in cik_get_allowed_info_register()
3717 	WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70);  in cik_gpu_init()
5204 		RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));  in cik_print_gpu_status_regs()
5258 	tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);  in cik_gpu_check_soft_reset()
5346 		tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);  in cik_gpu_soft_reset()
5348 		WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);  in cik_gpu_soft_reset()
5549 	tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);  in cik_gpu_pci_config_reset()
5551 	WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);  in cik_gpu_pci_config_reset()
5920 		WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0);  in cik_pcie_gart_enable()
5921 		WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0);  in cik_pcie_gart_enable()
6581 		WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);  in cik_enable_sdma_mgcg()
6584 		orig = data = RREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);  in cik_enable_sdma_mgcg()
6587 			WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);  in cik_enable_sdma_mgcg()
6602 		orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);  in cik_enable_sdma_mgls()
6605 			WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);  in cik_enable_sdma_mgls()
6612 		orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);  in cik_enable_sdma_mgls()
6615 			WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);  in cik_enable_sdma_mgls()
7287 	tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;  in cik_disable_interrupt_state()
7288 	WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);  in cik_disable_interrupt_state()
7471 	dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;  in cik_irq_set()
7581 	WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);  in cik_irq_set()