Lines Matching defs:hqd_registers
4829 struct hqd_registers struct
4831 u32 cp_mqd_base_addr;
4832 u32 cp_mqd_base_addr_hi;
4833 u32 cp_hqd_active;
4834 u32 cp_hqd_vmid;
4835 u32 cp_hqd_persistent_state;
4836 u32 cp_hqd_pipe_priority;
4837 u32 cp_hqd_queue_priority;
4838 u32 cp_hqd_quantum;
4839 u32 cp_hqd_pq_base;
4840 u32 cp_hqd_pq_base_hi;
4841 u32 cp_hqd_pq_rptr;
4842 u32 cp_hqd_pq_rptr_report_addr;
4843 u32 cp_hqd_pq_rptr_report_addr_hi;
4844 u32 cp_hqd_pq_wptr_poll_addr;
4845 u32 cp_hqd_pq_wptr_poll_addr_hi;
4846 u32 cp_hqd_pq_doorbell_control;
4847 u32 cp_hqd_pq_wptr;
4848 u32 cp_hqd_pq_control;
4849 u32 cp_hqd_ib_base_addr;
4850 u32 cp_hqd_ib_base_addr_hi;
4851 u32 cp_hqd_ib_rptr;
4852 u32 cp_hqd_ib_control;
4853 u32 cp_hqd_iq_timer;
4854 u32 cp_hqd_iq_rptr;
4855 u32 cp_hqd_dequeue_request;
4856 u32 cp_hqd_dma_offload;
4857 u32 cp_hqd_sema_cmd;
4858 u32 cp_hqd_msg_type;
4859 u32 cp_hqd_atomic0_preop_lo;
4860 u32 cp_hqd_atomic0_preop_hi;
4861 u32 cp_hqd_atomic1_preop_lo;
4862 u32 cp_hqd_atomic1_preop_hi;
4863 u32 cp_hqd_hq_scheduler0;
4864 u32 cp_hqd_hq_scheduler1;
4865 u32 cp_mqd_control;