Lines Matching refs:table
1296 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits() local
1302 table->FpsHighT = cpu_to_be16(tmp); in ci_init_fps_limits()
1305 table->FpsLowT = cpu_to_be16(tmp); in ci_init_fps_limits()
2189 SMU7_Discrete_DpmTable *table) in ci_populate_smc_vddc_table() argument
2194 table->VddcLevelCount = pi->vddc_voltage_table.count; in ci_populate_smc_vddc_table()
2195 for (count = 0; count < table->VddcLevelCount; count++) { in ci_populate_smc_vddc_table()
2198 &table->VddcLevel[count]); in ci_populate_smc_vddc_table()
2201 table->VddcLevel[count].Smio |= in ci_populate_smc_vddc_table()
2204 table->VddcLevel[count].Smio = 0; in ci_populate_smc_vddc_table()
2206 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount); in ci_populate_smc_vddc_table()
2212 SMU7_Discrete_DpmTable *table) in ci_populate_smc_vddci_table() argument
2217 table->VddciLevelCount = pi->vddci_voltage_table.count; in ci_populate_smc_vddci_table()
2218 for (count = 0; count < table->VddciLevelCount; count++) { in ci_populate_smc_vddci_table()
2221 &table->VddciLevel[count]); in ci_populate_smc_vddci_table()
2224 table->VddciLevel[count].Smio |= in ci_populate_smc_vddci_table()
2227 table->VddciLevel[count].Smio = 0; in ci_populate_smc_vddci_table()
2229 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount); in ci_populate_smc_vddci_table()
2235 SMU7_Discrete_DpmTable *table) in ci_populate_smc_mvdd_table() argument
2240 table->MvddLevelCount = pi->mvdd_voltage_table.count; in ci_populate_smc_mvdd_table()
2241 for (count = 0; count < table->MvddLevelCount; count++) { in ci_populate_smc_mvdd_table()
2244 &table->MvddLevel[count]); in ci_populate_smc_mvdd_table()
2247 table->MvddLevel[count].Smio |= in ci_populate_smc_mvdd_table()
2250 table->MvddLevel[count].Smio = 0; in ci_populate_smc_mvdd_table()
2252 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount); in ci_populate_smc_mvdd_table()
2258 SMU7_Discrete_DpmTable *table) in ci_populate_smc_voltage_tables() argument
2262 ret = ci_populate_smc_vddc_table(rdev, table); in ci_populate_smc_voltage_tables()
2266 ret = ci_populate_smc_vddci_table(rdev, table); in ci_populate_smc_voltage_tables()
2270 ret = ci_populate_smc_mvdd_table(rdev, table); in ci_populate_smc_voltage_tables()
2597 SMU7_Discrete_DpmTable *table) in ci_populate_smc_link_level() argument
2604 table->LinkLevel[i].PcieGenSpeed = in ci_populate_smc_link_level()
2606 table->LinkLevel[i].PcieLaneCount = in ci_populate_smc_link_level()
2608 table->LinkLevel[i].EnabledForActivity = 1; in ci_populate_smc_link_level()
2609 table->LinkLevel[i].DownT = cpu_to_be32(5); in ci_populate_smc_link_level()
2610 table->LinkLevel[i].UpT = cpu_to_be32(30); in ci_populate_smc_link_level()
2619 SMU7_Discrete_DpmTable *table) in ci_populate_smc_uvd_level() argument
2625 table->UvdLevelCount = in ci_populate_smc_uvd_level()
2628 for (count = 0; count < table->UvdLevelCount; count++) { in ci_populate_smc_uvd_level()
2629 table->UvdLevel[count].VclkFrequency = in ci_populate_smc_uvd_level()
2631 table->UvdLevel[count].DclkFrequency = in ci_populate_smc_uvd_level()
2633 table->UvdLevel[count].MinVddc = in ci_populate_smc_uvd_level()
2635 table->UvdLevel[count].MinVddcPhases = 1; in ci_populate_smc_uvd_level()
2639 table->UvdLevel[count].VclkFrequency, false, ÷rs); in ci_populate_smc_uvd_level()
2643 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2647 table->UvdLevel[count].DclkFrequency, false, ÷rs); in ci_populate_smc_uvd_level()
2651 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider; in ci_populate_smc_uvd_level()
2653 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency); in ci_populate_smc_uvd_level()
2654 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency); in ci_populate_smc_uvd_level()
2655 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc); in ci_populate_smc_uvd_level()
2662 SMU7_Discrete_DpmTable *table) in ci_populate_smc_vce_level() argument
2668 table->VceLevelCount = in ci_populate_smc_vce_level()
2671 for (count = 0; count < table->VceLevelCount; count++) { in ci_populate_smc_vce_level()
2672 table->VceLevel[count].Frequency = in ci_populate_smc_vce_level()
2674 table->VceLevel[count].MinVoltage = in ci_populate_smc_vce_level()
2676 table->VceLevel[count].MinPhases = 1; in ci_populate_smc_vce_level()
2680 table->VceLevel[count].Frequency, false, ÷rs); in ci_populate_smc_vce_level()
2684 table->VceLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_vce_level()
2686 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency); in ci_populate_smc_vce_level()
2687 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage); in ci_populate_smc_vce_level()
2695 SMU7_Discrete_DpmTable *table) in ci_populate_smc_acp_level() argument
2701 table->AcpLevelCount = (u8) in ci_populate_smc_acp_level()
2704 for (count = 0; count < table->AcpLevelCount; count++) { in ci_populate_smc_acp_level()
2705 table->AcpLevel[count].Frequency = in ci_populate_smc_acp_level()
2707 table->AcpLevel[count].MinVoltage = in ci_populate_smc_acp_level()
2709 table->AcpLevel[count].MinPhases = 1; in ci_populate_smc_acp_level()
2713 table->AcpLevel[count].Frequency, false, ÷rs); in ci_populate_smc_acp_level()
2717 table->AcpLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_acp_level()
2719 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency); in ci_populate_smc_acp_level()
2720 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage); in ci_populate_smc_acp_level()
2727 SMU7_Discrete_DpmTable *table) in ci_populate_smc_samu_level() argument
2733 table->SamuLevelCount = in ci_populate_smc_samu_level()
2736 for (count = 0; count < table->SamuLevelCount; count++) { in ci_populate_smc_samu_level()
2737 table->SamuLevel[count].Frequency = in ci_populate_smc_samu_level()
2739 table->SamuLevel[count].MinVoltage = in ci_populate_smc_samu_level()
2741 table->SamuLevel[count].MinPhases = 1; in ci_populate_smc_samu_level()
2745 table->SamuLevel[count].Frequency, false, ÷rs); in ci_populate_smc_samu_level()
2749 table->SamuLevel[count].Divider = (u8)dividers.post_divider; in ci_populate_smc_samu_level()
2751 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency); in ci_populate_smc_samu_level()
2752 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage); in ci_populate_smc_samu_level()
2960 SMU7_Discrete_DpmTable *table) in ci_populate_smc_acpi_level() argument
2971 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; in ci_populate_smc_acpi_level()
2974 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2976 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
2978 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
2980 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq; in ci_populate_smc_acpi_level()
2984 table->ACPILevel.SclkFrequency, false, ÷rs); in ci_populate_smc_acpi_level()
2988 table->ACPILevel.SclkDid = (u8)dividers.post_divider; in ci_populate_smc_acpi_level()
2989 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; in ci_populate_smc_acpi_level()
2990 table->ACPILevel.DeepSleepDivId = 0; in ci_populate_smc_acpi_level()
2998 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; in ci_populate_smc_acpi_level()
2999 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; in ci_populate_smc_acpi_level()
3000 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_populate_smc_acpi_level()
3001 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_populate_smc_acpi_level()
3002 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_populate_smc_acpi_level()
3003 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_populate_smc_acpi_level()
3004 table->ACPILevel.CcPwrDynRm = 0; in ci_populate_smc_acpi_level()
3005 table->ACPILevel.CcPwrDynRm1 = 0; in ci_populate_smc_acpi_level()
3007 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags); in ci_populate_smc_acpi_level()
3008 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases); in ci_populate_smc_acpi_level()
3009 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency); in ci_populate_smc_acpi_level()
3010 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl); in ci_populate_smc_acpi_level()
3011 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2); in ci_populate_smc_acpi_level()
3012 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3); in ci_populate_smc_acpi_level()
3013 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4); in ci_populate_smc_acpi_level()
3014 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum); in ci_populate_smc_acpi_level()
3015 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2); in ci_populate_smc_acpi_level()
3016 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm); in ci_populate_smc_acpi_level()
3017 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1); in ci_populate_smc_acpi_level()
3019 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc; in ci_populate_smc_acpi_level()
3020 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases; in ci_populate_smc_acpi_level()
3024 table->MemoryACPILevel.MinVddci = in ci_populate_smc_acpi_level()
3027 table->MemoryACPILevel.MinVddci = in ci_populate_smc_acpi_level()
3032 table->MemoryACPILevel.MinMvdd = 0; in ci_populate_smc_acpi_level()
3034 table->MemoryACPILevel.MinMvdd = in ci_populate_smc_acpi_level()
3042 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl); in ci_populate_smc_acpi_level()
3043 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl); in ci_populate_smc_acpi_level()
3044 table->MemoryACPILevel.MpllAdFuncCntl = in ci_populate_smc_acpi_level()
3046 table->MemoryACPILevel.MpllDqFuncCntl = in ci_populate_smc_acpi_level()
3048 table->MemoryACPILevel.MpllFuncCntl = in ci_populate_smc_acpi_level()
3050 table->MemoryACPILevel.MpllFuncCntl_1 = in ci_populate_smc_acpi_level()
3052 table->MemoryACPILevel.MpllFuncCntl_2 = in ci_populate_smc_acpi_level()
3054 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); in ci_populate_smc_acpi_level()
3055 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); in ci_populate_smc_acpi_level()
3057 table->MemoryACPILevel.EnabledForThrottle = 0; in ci_populate_smc_acpi_level()
3058 table->MemoryACPILevel.EnabledForActivity = 0; in ci_populate_smc_acpi_level()
3059 table->MemoryACPILevel.UpH = 0; in ci_populate_smc_acpi_level()
3060 table->MemoryACPILevel.DownH = 100; in ci_populate_smc_acpi_level()
3061 table->MemoryACPILevel.VoltageDownH = 0; in ci_populate_smc_acpi_level()
3062 table->MemoryACPILevel.ActivityLevel = in ci_populate_smc_acpi_level()
3065 table->MemoryACPILevel.StutterEnable = false; in ci_populate_smc_acpi_level()
3066 table->MemoryACPILevel.StrobeEnable = false; in ci_populate_smc_acpi_level()
3067 table->MemoryACPILevel.EdcReadEnable = false; in ci_populate_smc_acpi_level()
3068 table->MemoryACPILevel.EdcWriteEnable = false; in ci_populate_smc_acpi_level()
3069 table->MemoryACPILevel.RttEnable = false; in ci_populate_smc_acpi_level()
3509 static int ci_find_boot_level(struct ci_single_dpm_table *table, in ci_find_boot_level() argument
3515 for(i = 0; i < table->count; i++) { in ci_find_boot_level()
3516 if (value == table->dpm_levels[i].value) { in ci_find_boot_level()
3530 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_smc_table() local
3538 ci_populate_smc_voltage_tables(rdev, table); in ci_init_smc_table()
3543 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; in ci_init_smc_table()
3546 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; in ci_init_smc_table()
3549 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; in ci_init_smc_table()
3566 ci_populate_smc_link_level(rdev, table); in ci_init_smc_table()
3568 ret = ci_populate_smc_acpi_level(rdev, table); in ci_init_smc_table()
3572 ret = ci_populate_smc_vce_level(rdev, table); in ci_init_smc_table()
3576 ret = ci_populate_smc_acp_level(rdev, table); in ci_init_smc_table()
3580 ret = ci_populate_smc_samu_level(rdev, table); in ci_init_smc_table()
3588 ret = ci_populate_smc_uvd_level(rdev, table); in ci_init_smc_table()
3592 table->UvdBootLevel = 0; in ci_init_smc_table()
3593 table->VceBootLevel = 0; in ci_init_smc_table()
3594 table->AcpBootLevel = 0; in ci_init_smc_table()
3595 table->SamuBootLevel = 0; in ci_init_smc_table()
3596 table->GraphicsBootLevel = 0; in ci_init_smc_table()
3597 table->MemoryBootLevel = 0; in ci_init_smc_table()
3607 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; in ci_init_smc_table()
3608 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; in ci_init_smc_table()
3609 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; in ci_init_smc_table()
3617 table->UVDInterval = 1; in ci_init_smc_table()
3618 table->VCEInterval = 1; in ci_init_smc_table()
3619 table->ACPInterval = 1; in ci_init_smc_table()
3620 table->SAMUInterval = 1; in ci_init_smc_table()
3621 table->GraphicsVoltageChangeEnable = 1; in ci_init_smc_table()
3622 table->GraphicsThermThrottleEnable = 1; in ci_init_smc_table()
3623 table->GraphicsInterval = 1; in ci_init_smc_table()
3624 table->VoltageInterval = 1; in ci_init_smc_table()
3625 table->ThermalInterval = 1; in ci_init_smc_table()
3626 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * in ci_init_smc_table()
3628 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * in ci_init_smc_table()
3630 table->MemoryVoltageChangeEnable = 1; in ci_init_smc_table()
3631 table->MemoryInterval = 1; in ci_init_smc_table()
3632 table->VoltageResponseTime = 0; in ci_init_smc_table()
3633 table->VddcVddciDelta = 4000; in ci_init_smc_table()
3634 table->PhaseResponseTime = 0; in ci_init_smc_table()
3635 table->MemoryThermThrottleEnable = 1; in ci_init_smc_table()
3636 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; in ci_init_smc_table()
3637 table->PCIeGenInterval = 1; in ci_init_smc_table()
3639 table->SVI2Enable = 1; in ci_init_smc_table()
3641 table->SVI2Enable = 0; in ci_init_smc_table()
3643 table->ThermGpio = 17; in ci_init_smc_table()
3644 table->SclkStepSize = 0x4000; in ci_init_smc_table()
3646 table->SystemFlags = cpu_to_be32(table->SystemFlags); in ci_init_smc_table()
3647 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid); in ci_init_smc_table()
3648 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase); in ci_init_smc_table()
3649 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid); in ci_init_smc_table()
3650 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid); in ci_init_smc_table()
3651 table->SclkStepSize = cpu_to_be32(table->SclkStepSize); in ci_init_smc_table()
3652 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh); in ci_init_smc_table()
3653 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow); in ci_init_smc_table()
3654 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta); in ci_init_smc_table()
3655 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime); in ci_init_smc_table()
3656 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime); in ci_init_smc_table()
3657 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE); in ci_init_smc_table()
3658 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE); in ci_init_smc_table()
3659 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE); in ci_init_smc_table()
3664 (u8 *)&table->SystemFlags, in ci_init_smc_table()
4070 struct radeon_vce_clock_voltage_dependency_table *table = in ci_get_vce_boot_level() local
4073 for (i = 0; i < table->count; i++) { in ci_get_vce_boot_level()
4074 if (table->entries[i].evclk >= min_evclk) in ci_get_vce_boot_level()
4078 return table->count - 1; in ci_get_vce_boot_level()
4304 struct ci_mc_reg_table *table) in ci_set_mc_special_registers() argument
4310 for (i = 0, j = table->last; i < table->last; i++) { in ci_set_mc_special_registers()
4313 switch(table->mc_reg_address[i].s1 << 2) { in ci_set_mc_special_registers()
4316 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; in ci_set_mc_special_registers()
4317 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in ci_set_mc_special_registers()
4318 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4319 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
4320 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); in ci_set_mc_special_registers()
4327 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; in ci_set_mc_special_registers()
4328 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; in ci_set_mc_special_registers()
4329 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4330 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
4331 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ci_set_mc_special_registers()
4333 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; in ci_set_mc_special_registers()
4340 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; in ci_set_mc_special_registers()
4341 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; in ci_set_mc_special_registers()
4342 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4343 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
4344 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; in ci_set_mc_special_registers()
4353 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; in ci_set_mc_special_registers()
4354 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; in ci_set_mc_special_registers()
4355 for (k = 0; k < table->num_entries; k++) { in ci_set_mc_special_registers()
4356 table->mc_reg_table_entry[k].mc_data[j] = in ci_set_mc_special_registers()
4357 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); in ci_set_mc_special_registers()
4369 table->last = j; in ci_set_mc_special_registers()
4447 static void ci_set_valid_flag(struct ci_mc_reg_table *table) in ci_set_valid_flag() argument
4451 for (i = 0; i < table->last; i++) { in ci_set_valid_flag()
4452 for (j = 1; j < table->num_entries; j++) { in ci_set_valid_flag()
4453 if (table->mc_reg_table_entry[j-1].mc_data[i] != in ci_set_valid_flag()
4454 table->mc_reg_table_entry[j].mc_data[i]) { in ci_set_valid_flag()
4455 table->valid_flag |= 1 << i; in ci_set_valid_flag()
4462 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table) in ci_set_s0_mc_reg_index() argument
4467 for (i = 0; i < table->last; i++) { in ci_set_s0_mc_reg_index()
4468 table->mc_reg_address[i].s0 = in ci_set_s0_mc_reg_index()
4469 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? in ci_set_s0_mc_reg_index()
4470 address : table->mc_reg_address[i].s1; in ci_set_s0_mc_reg_index()
4474 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table, in ci_copy_vbios_mc_reg_table() argument
4479 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) in ci_copy_vbios_mc_reg_table()
4481 if (table->num_entries > MAX_AC_TIMING_ENTRIES) in ci_copy_vbios_mc_reg_table()
4484 for (i = 0; i < table->last; i++) in ci_copy_vbios_mc_reg_table()
4485 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; in ci_copy_vbios_mc_reg_table()
4487 ci_table->last = table->last; in ci_copy_vbios_mc_reg_table()
4489 for (i = 0; i < table->num_entries; i++) { in ci_copy_vbios_mc_reg_table()
4491 table->mc_reg_table_entry[i].mclk_max; in ci_copy_vbios_mc_reg_table()
4492 for (j = 0; j < table->last; j++) in ci_copy_vbios_mc_reg_table()
4494 table->mc_reg_table_entry[i].mc_data[j]; in ci_copy_vbios_mc_reg_table()
4496 ci_table->num_entries = table->num_entries; in ci_copy_vbios_mc_reg_table()
4502 struct ci_mc_reg_table *table) in ci_register_patching_mc_seq() argument
4514 for (i = 0; i < table->last; i++) { in ci_register_patching_mc_seq()
4515 if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) in ci_register_patching_mc_seq()
4517 switch(table->mc_reg_address[i].s1 >> 2) { in ci_register_patching_mc_seq()
4519 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4520 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || in ci_register_patching_mc_seq()
4521 (table->mc_reg_table_entry[k].mclk_max == 137500)) in ci_register_patching_mc_seq()
4522 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4523 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) | in ci_register_patching_mc_seq()
4528 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4529 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || in ci_register_patching_mc_seq()
4530 (table->mc_reg_table_entry[k].mclk_max == 137500)) in ci_register_patching_mc_seq()
4531 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4532 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | in ci_register_patching_mc_seq()
4537 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4538 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || in ci_register_patching_mc_seq()
4539 (table->mc_reg_table_entry[k].mclk_max == 137500)) in ci_register_patching_mc_seq()
4540 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4541 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) | in ci_register_patching_mc_seq()
4546 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4547 if ((table->mc_reg_table_entry[k].mclk_max == 125000) || in ci_register_patching_mc_seq()
4548 (table->mc_reg_table_entry[k].mclk_max == 137500)) in ci_register_patching_mc_seq()
4549 table->mc_reg_table_entry[k].mc_data[i] = 0; in ci_register_patching_mc_seq()
4553 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4554 if (table->mc_reg_table_entry[k].mclk_max == 125000) in ci_register_patching_mc_seq()
4555 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4556 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | in ci_register_patching_mc_seq()
4558 else if (table->mc_reg_table_entry[k].mclk_max == 137500) in ci_register_patching_mc_seq()
4559 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4560 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) | in ci_register_patching_mc_seq()
4565 for (k = 0; k < table->num_entries; k++) { in ci_register_patching_mc_seq()
4566 if (table->mc_reg_table_entry[k].mclk_max == 125000) in ci_register_patching_mc_seq()
4567 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4568 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | in ci_register_patching_mc_seq()
4570 else if (table->mc_reg_table_entry[k].mclk_max == 137500) in ci_register_patching_mc_seq()
4571 table->mc_reg_table_entry[k].mc_data[i] = in ci_register_patching_mc_seq()
4572 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) | in ci_register_patching_mc_seq()
4594 struct atom_mc_reg_table *table; in ci_initialize_mc_reg_table() local
4599 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); in ci_initialize_mc_reg_table()
4600 if (!table) in ci_initialize_mc_reg_table()
4624 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); in ci_initialize_mc_reg_table()
4628 ret = ci_copy_vbios_mc_reg_table(table, ci_table); in ci_initialize_mc_reg_table()
4645 kfree(table); in ci_initialize_mc_reg_table()
4954 struct radeon_clock_voltage_dependency_table *table) in ci_patch_clock_voltage_dependency_table_with_vddc_leakage() argument
4958 if (table) { in ci_patch_clock_voltage_dependency_table_with_vddc_leakage()
4959 for (i = 0; i < table->count; i++) in ci_patch_clock_voltage_dependency_table_with_vddc_leakage()
4960 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); in ci_patch_clock_voltage_dependency_table_with_vddc_leakage()
4965 struct radeon_clock_voltage_dependency_table *table) in ci_patch_clock_voltage_dependency_table_with_vddci_leakage() argument
4969 if (table) { in ci_patch_clock_voltage_dependency_table_with_vddci_leakage()
4970 for (i = 0; i < table->count; i++) in ci_patch_clock_voltage_dependency_table_with_vddci_leakage()
4971 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v); in ci_patch_clock_voltage_dependency_table_with_vddci_leakage()
4976 struct radeon_vce_clock_voltage_dependency_table *table) in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage() argument
4980 if (table) { in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage()
4981 for (i = 0; i < table->count; i++) in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage()
4982 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage()
4987 struct radeon_uvd_clock_voltage_dependency_table *table) in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage() argument
4991 if (table) { in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage()
4992 for (i = 0; i < table->count; i++) in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage()
4993 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage()
4998 struct radeon_phase_shedding_limits_table *table) in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage() argument
5002 if (table) { in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage()
5003 for (i = 0; i < table->count; i++) in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage()
5004 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage); in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage()
5009 struct radeon_clock_and_voltage_limits *table) in ci_patch_clock_voltage_limits_with_vddc_leakage() argument
5011 if (table) { in ci_patch_clock_voltage_limits_with_vddc_leakage()
5012 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc); in ci_patch_clock_voltage_limits_with_vddc_leakage()
5013 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci); in ci_patch_clock_voltage_limits_with_vddc_leakage()
5018 struct radeon_cac_leakage_table *table) in ci_patch_cac_leakage_table_with_vddc_leakage() argument
5022 if (table) { in ci_patch_cac_leakage_table_with_vddc_leakage()
5023 for (i = 0; i < table->count; i++) in ci_patch_cac_leakage_table_with_vddc_leakage()
5024 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc); in ci_patch_cac_leakage_table_with_vddc_leakage()