Lines Matching refs:rdev
165 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
166 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
170 extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
173 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
174 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
175 extern int ci_mc_load_microcode(struct radeon_device *rdev);
176 extern void cik_update_cg(struct radeon_device *rdev,
179 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
182 static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
183 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
185 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
187 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
190 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev);
191 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev);
193 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev) in ci_get_pi() argument
195 struct ci_power_info *pi = rdev->pm.dpm.priv; in ci_get_pi()
207 static void ci_initialize_powertune_defaults(struct radeon_device *rdev) in ci_initialize_powertune_defaults() argument
209 struct ci_power_info *pi = ci_get_pi(rdev); in ci_initialize_powertune_defaults()
211 switch (rdev->pdev->device) { in ci_initialize_powertune_defaults()
258 if (rdev->family == CHIP_HAWAII) in ci_initialize_powertune_defaults()
272 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev) in ci_populate_bapm_vddc_vid_sidd() argument
274 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_vddc_vid_sidd()
280 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) in ci_populate_bapm_vddc_vid_sidd()
282 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8) in ci_populate_bapm_vddc_vid_sidd()
284 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count != in ci_populate_bapm_vddc_vid_sidd()
285 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) in ci_populate_bapm_vddc_vid_sidd()
288 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { in ci_populate_bapm_vddc_vid_sidd()
289 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in ci_populate_bapm_vddc_vid_sidd()
290 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); in ci_populate_bapm_vddc_vid_sidd()
291 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); in ci_populate_bapm_vddc_vid_sidd()
292 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); in ci_populate_bapm_vddc_vid_sidd()
294 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc); in ci_populate_bapm_vddc_vid_sidd()
295 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage); in ci_populate_bapm_vddc_vid_sidd()
301 static int ci_populate_vddc_vid(struct radeon_device *rdev) in ci_populate_vddc_vid() argument
303 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_vddc_vid()
316 static int ci_populate_svi_load_line(struct radeon_device *rdev) in ci_populate_svi_load_line() argument
318 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_svi_load_line()
329 static int ci_populate_tdc_limit(struct radeon_device *rdev) in ci_populate_tdc_limit() argument
331 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_tdc_limit()
335 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256; in ci_populate_tdc_limit()
344 static int ci_populate_dw8(struct radeon_device *rdev) in ci_populate_dw8() argument
346 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_dw8()
350 ret = ci_read_smc_sram_dword(rdev, in ci_populate_dw8()
364 static int ci_populate_fuzzy_fan(struct radeon_device *rdev) in ci_populate_fuzzy_fan() argument
366 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_fuzzy_fan()
368 if ((rdev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) || in ci_populate_fuzzy_fan()
369 (rdev->pm.dpm.fan.fan_output_sensitivity == 0)) in ci_populate_fuzzy_fan()
370 rdev->pm.dpm.fan.fan_output_sensitivity = in ci_populate_fuzzy_fan()
371 rdev->pm.dpm.fan.default_fan_output_sensitivity; in ci_populate_fuzzy_fan()
374 cpu_to_be16(rdev->pm.dpm.fan.fan_output_sensitivity); in ci_populate_fuzzy_fan()
379 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev) in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc() argument
381 struct ci_power_info *pi = ci_get_pi(rdev); in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
411 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev) in ci_populate_bapm_vddc_base_leakage_sidd() argument
413 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_vddc_base_leakage_sidd()
417 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_vddc_base_leakage_sidd()
428 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev) in ci_populate_bapm_parameters_in_dpm_table() argument
430 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_parameters_in_dpm_table()
434 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_parameters_in_dpm_table()
435 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; in ci_populate_bapm_parameters_in_dpm_table()
476 static int ci_populate_pm_base(struct radeon_device *rdev) in ci_populate_pm_base() argument
478 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_pm_base()
483 ret = ci_read_smc_sram_dword(rdev, in ci_populate_pm_base()
489 ret = ci_populate_bapm_vddc_vid_sidd(rdev); in ci_populate_pm_base()
492 ret = ci_populate_vddc_vid(rdev); in ci_populate_pm_base()
495 ret = ci_populate_svi_load_line(rdev); in ci_populate_pm_base()
498 ret = ci_populate_tdc_limit(rdev); in ci_populate_pm_base()
501 ret = ci_populate_dw8(rdev); in ci_populate_pm_base()
504 ret = ci_populate_fuzzy_fan(rdev); in ci_populate_pm_base()
507 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev); in ci_populate_pm_base()
510 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev); in ci_populate_pm_base()
513 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset, in ci_populate_pm_base()
523 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable) in ci_do_enable_didt() argument
525 struct ci_power_info *pi = ci_get_pi(rdev); in ci_do_enable_didt()
565 static int ci_program_pt_config_registers(struct radeon_device *rdev, in ci_program_pt_config_registers() argument
613 static int ci_enable_didt(struct radeon_device *rdev, bool enable) in ci_enable_didt() argument
615 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_didt()
620 cik_enter_rlc_safe_mode(rdev); in ci_enable_didt()
623 ret = ci_program_pt_config_registers(rdev, didt_config_ci); in ci_enable_didt()
625 cik_exit_rlc_safe_mode(rdev); in ci_enable_didt()
630 ci_do_enable_didt(rdev, enable); in ci_enable_didt()
632 cik_exit_rlc_safe_mode(rdev); in ci_enable_didt()
638 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable) in ci_enable_power_containment() argument
640 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_power_containment()
648 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); in ci_enable_power_containment()
656 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable); in ci_enable_power_containment()
664 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable); in ci_enable_power_containment()
669 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_enable_power_containment()
675 ci_set_power_limit(rdev, default_pwr_limit); in ci_enable_power_containment()
682 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable); in ci_enable_power_containment()
685 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); in ci_enable_power_containment()
688 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable); in ci_enable_power_containment()
696 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable) in ci_enable_smc_cac() argument
698 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_smc_cac()
704 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); in ci_enable_smc_cac()
712 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); in ci_enable_smc_cac()
720 static int ci_enable_thermal_based_sclk_dpm(struct radeon_device *rdev, in ci_enable_thermal_based_sclk_dpm() argument
723 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_thermal_based_sclk_dpm()
728 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_ENABLE_THERMAL_DPM); in ci_enable_thermal_based_sclk_dpm()
730 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DISABLE_THERMAL_DPM); in ci_enable_thermal_based_sclk_dpm()
739 static int ci_power_control_set_level(struct radeon_device *rdev) in ci_power_control_set_level() argument
741 struct ci_power_info *pi = ci_get_pi(rdev); in ci_power_control_set_level()
743 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_power_control_set_level()
751 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment); in ci_power_control_set_level()
755 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp); in ci_power_control_set_level()
761 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate) in ci_dpm_powergate_uvd() argument
763 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_powergate_uvd()
770 ci_update_uvd_dpm(rdev, gate); in ci_dpm_powergate_uvd()
773 bool ci_dpm_vblank_too_short(struct radeon_device *rdev) in ci_dpm_vblank_too_short() argument
775 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_vblank_too_short()
776 u32 vblank_time = r600_dpm_get_vblank_time(rdev); in ci_dpm_vblank_too_short()
786 static void ci_apply_state_adjust_rules(struct radeon_device *rdev, in ci_apply_state_adjust_rules() argument
790 struct ci_power_info *pi = ci_get_pi(rdev); in ci_apply_state_adjust_rules()
797 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in ci_apply_state_adjust_rules()
798 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in ci_apply_state_adjust_rules()
804 if ((rdev->pm.dpm.new_active_crtc_count > 1) || in ci_apply_state_adjust_rules()
805 ci_dpm_vblank_too_short(rdev)) in ci_apply_state_adjust_rules()
815 if (rdev->pm.dpm.ac_power) in ci_apply_state_adjust_rules()
816 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_apply_state_adjust_rules()
818 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_apply_state_adjust_rules()
820 if (rdev->pm.dpm.ac_power == false) { in ci_apply_state_adjust_rules()
840 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) in ci_apply_state_adjust_rules()
841 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; in ci_apply_state_adjust_rules()
842 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) in ci_apply_state_adjust_rules()
843 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; in ci_apply_state_adjust_rules()
861 static int ci_thermal_set_temperature_range(struct radeon_device *rdev, in ci_thermal_set_temperature_range() argument
891 rdev->pm.dpm.thermal.min_temp = low_temp; in ci_thermal_set_temperature_range()
892 rdev->pm.dpm.thermal.max_temp = high_temp; in ci_thermal_set_temperature_range()
897 static int ci_thermal_enable_alert(struct radeon_device *rdev, in ci_thermal_enable_alert() argument
906 rdev->irq.dpm_thermal = false; in ci_thermal_enable_alert()
907 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Enable); in ci_thermal_enable_alert()
915 rdev->irq.dpm_thermal = true; in ci_thermal_enable_alert()
916 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Disable); in ci_thermal_enable_alert()
926 static void ci_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) in ci_fan_ctrl_set_static_mode() argument
928 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_static_mode()
948 static int ci_thermal_setup_fan_table(struct radeon_device *rdev) in ci_thermal_setup_fan_table() argument
950 struct ci_power_info *pi = ci_get_pi(rdev); in ci_thermal_setup_fan_table()
960 rdev->pm.dpm.fan.ucode_fan_control = false; in ci_thermal_setup_fan_table()
967 rdev->pm.dpm.fan.ucode_fan_control = false; in ci_thermal_setup_fan_table()
971 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; in ci_thermal_setup_fan_table()
975 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; in ci_thermal_setup_fan_table()
976 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; in ci_thermal_setup_fan_table()
978 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; in ci_thermal_setup_fan_table()
979 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; in ci_thermal_setup_fan_table()
984 fan_table.TempMin = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); in ci_thermal_setup_fan_table()
985 fan_table.TempMed = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); in ci_thermal_setup_fan_table()
986 fan_table.TempMax = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); in ci_thermal_setup_fan_table()
993 fan_table.HystDown = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); in ci_thermal_setup_fan_table()
1001 reference_clock = radeon_get_xclk(rdev); in ci_thermal_setup_fan_table()
1003 fan_table.RefreshPeriod = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * in ci_thermal_setup_fan_table()
1011 ret = ci_copy_bytes_to_smc(rdev, in ci_thermal_setup_fan_table()
1019 rdev->pm.dpm.fan.ucode_fan_control = false; in ci_thermal_setup_fan_table()
1025 static int ci_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) in ci_fan_ctrl_start_smc_fan_control() argument
1027 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_start_smc_fan_control()
1031 ret = ci_send_msg_to_smc_with_parameter(rdev, in ci_fan_ctrl_start_smc_fan_control()
1036 ret = ci_send_msg_to_smc_with_parameter(rdev, in ci_fan_ctrl_start_smc_fan_control()
1038 rdev->pm.dpm.fan.default_max_fan_pwm); in ci_fan_ctrl_start_smc_fan_control()
1042 ret = ci_send_msg_to_smc_with_parameter(rdev, in ci_fan_ctrl_start_smc_fan_control()
1053 static int ci_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) in ci_fan_ctrl_stop_smc_fan_control() argument
1056 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_stop_smc_fan_control()
1058 ret = ci_send_msg_to_smc(rdev, PPSMC_StopFanControl); in ci_fan_ctrl_stop_smc_fan_control()
1066 int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, in ci_fan_ctrl_get_fan_speed_percent() argument
1072 if (rdev->pm.no_fan) in ci_fan_ctrl_get_fan_speed_percent()
1091 int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, in ci_fan_ctrl_set_fan_speed_percent() argument
1097 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_fan_speed_percent()
1099 if (rdev->pm.no_fan) in ci_fan_ctrl_set_fan_speed_percent()
1124 void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) in ci_fan_ctrl_set_mode() argument
1128 if (rdev->pm.dpm.fan.ucode_fan_control) in ci_fan_ctrl_set_mode()
1129 ci_fan_ctrl_stop_smc_fan_control(rdev); in ci_fan_ctrl_set_mode()
1130 ci_fan_ctrl_set_static_mode(rdev, mode); in ci_fan_ctrl_set_mode()
1133 if (rdev->pm.dpm.fan.ucode_fan_control) in ci_fan_ctrl_set_mode()
1134 ci_thermal_start_smc_fan_control(rdev); in ci_fan_ctrl_set_mode()
1136 ci_fan_ctrl_set_default_mode(rdev); in ci_fan_ctrl_set_mode()
1140 u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev) in ci_fan_ctrl_get_mode() argument
1142 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_get_mode()
1153 static int ci_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
1157 u32 xclk = radeon_get_xclk(rdev);
1159 if (rdev->pm.no_fan)
1162 if (rdev->pm.fan_pulses_per_revolution == 0)
1174 static int ci_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
1178 u32 xclk = radeon_get_xclk(rdev);
1180 if (rdev->pm.no_fan)
1183 if (rdev->pm.fan_pulses_per_revolution == 0)
1186 if ((speed < rdev->pm.fan_min_rpm) ||
1187 (speed > rdev->pm.fan_max_rpm))
1190 if (rdev->pm.dpm.fan.ucode_fan_control)
1191 ci_fan_ctrl_stop_smc_fan_control(rdev);
1198 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
1204 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev) in ci_fan_ctrl_set_default_mode() argument
1206 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_default_mode()
1221 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev) in ci_thermal_start_smc_fan_control() argument
1223 if (rdev->pm.dpm.fan.ucode_fan_control) { in ci_thermal_start_smc_fan_control()
1224 ci_fan_ctrl_start_smc_fan_control(rdev); in ci_thermal_start_smc_fan_control()
1225 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); in ci_thermal_start_smc_fan_control()
1229 static void ci_thermal_initialize(struct radeon_device *rdev) in ci_thermal_initialize() argument
1233 if (rdev->pm.fan_pulses_per_revolution) { in ci_thermal_initialize()
1235 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); in ci_thermal_initialize()
1244 static int ci_thermal_start_thermal_controller(struct radeon_device *rdev) in ci_thermal_start_thermal_controller() argument
1248 ci_thermal_initialize(rdev); in ci_thermal_start_thermal_controller()
1249 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); in ci_thermal_start_thermal_controller()
1252 ret = ci_thermal_enable_alert(rdev, true); in ci_thermal_start_thermal_controller()
1255 if (rdev->pm.dpm.fan.ucode_fan_control) { in ci_thermal_start_thermal_controller()
1256 ret = ci_thermal_setup_fan_table(rdev); in ci_thermal_start_thermal_controller()
1259 ci_thermal_start_smc_fan_control(rdev); in ci_thermal_start_thermal_controller()
1265 static void ci_thermal_stop_thermal_controller(struct radeon_device *rdev) in ci_thermal_stop_thermal_controller() argument
1267 if (!rdev->pm.no_fan) in ci_thermal_stop_thermal_controller()
1268 ci_fan_ctrl_set_default_mode(rdev); in ci_thermal_stop_thermal_controller()
1272 static int ci_read_smc_soft_register(struct radeon_device *rdev,
1275 struct ci_power_info *pi = ci_get_pi(rdev);
1277 return ci_read_smc_sram_dword(rdev,
1283 static int ci_write_smc_soft_register(struct radeon_device *rdev, in ci_write_smc_soft_register() argument
1286 struct ci_power_info *pi = ci_get_pi(rdev); in ci_write_smc_soft_register()
1288 return ci_write_smc_sram_dword(rdev, in ci_write_smc_soft_register()
1293 static void ci_init_fps_limits(struct radeon_device *rdev) in ci_init_fps_limits() argument
1295 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_fps_limits()
1309 static int ci_update_sclk_t(struct radeon_device *rdev) in ci_update_sclk_t() argument
1311 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_sclk_t()
1318 ret = ci_copy_bytes_to_smc(rdev, in ci_update_sclk_t()
1329 static void ci_get_leakage_voltages(struct radeon_device *rdev) in ci_get_leakage_voltages() argument
1331 struct ci_power_info *pi = ci_get_pi(rdev); in ci_get_leakage_voltages()
1339 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in ci_get_leakage_voltages()
1342 if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0) in ci_get_leakage_voltages()
1350 } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) { in ci_get_leakage_voltages()
1353 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci, in ci_get_leakage_voltages()
1371 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) in ci_set_dpm_event_sources() argument
1373 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_dpm_event_sources()
1420 static void ci_enable_auto_throttle_source(struct radeon_device *rdev, in ci_enable_auto_throttle_source() argument
1424 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_auto_throttle_source()
1429 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1434 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1439 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev) in ci_enable_vr_hot_gpio_interrupt() argument
1441 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) in ci_enable_vr_hot_gpio_interrupt()
1442 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt); in ci_enable_vr_hot_gpio_interrupt()
1445 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev) in ci_unfreeze_sclk_mclk_dpm() argument
1447 struct ci_power_info *pi = ci_get_pi(rdev); in ci_unfreeze_sclk_mclk_dpm()
1455 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel); in ci_unfreeze_sclk_mclk_dpm()
1462 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel); in ci_unfreeze_sclk_mclk_dpm()
1471 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable) in ci_enable_sclk_mclk_dpm() argument
1473 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_sclk_mclk_dpm()
1478 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable); in ci_enable_sclk_mclk_dpm()
1484 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable); in ci_enable_sclk_mclk_dpm()
1502 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable); in ci_enable_sclk_mclk_dpm()
1508 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable); in ci_enable_sclk_mclk_dpm()
1517 static int ci_start_dpm(struct radeon_device *rdev) in ci_start_dpm() argument
1519 struct ci_power_info *pi = ci_get_pi(rdev); in ci_start_dpm()
1532 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000); in ci_start_dpm()
1536 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable); in ci_start_dpm()
1540 ret = ci_enable_sclk_mclk_dpm(rdev, true); in ci_start_dpm()
1545 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable); in ci_start_dpm()
1553 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev) in ci_freeze_sclk_mclk_dpm() argument
1555 struct ci_power_info *pi = ci_get_pi(rdev); in ci_freeze_sclk_mclk_dpm()
1563 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel); in ci_freeze_sclk_mclk_dpm()
1570 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel); in ci_freeze_sclk_mclk_dpm()
1578 static int ci_stop_dpm(struct radeon_device *rdev) in ci_stop_dpm() argument
1580 struct ci_power_info *pi = ci_get_pi(rdev); in ci_stop_dpm()
1594 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable); in ci_stop_dpm()
1599 ret = ci_enable_sclk_mclk_dpm(rdev, false); in ci_stop_dpm()
1603 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable); in ci_stop_dpm()
1610 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable) in ci_enable_sclk_control() argument
1622 static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1625 struct ci_power_info *pi = ci_get_pi(rdev);
1627 rdev->pm.dpm.dyn_state.cac_tdp_table;
1635 ci_set_power_limit(rdev, power_limit);
1639 ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1641 ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1648 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev, in ci_send_msg_to_smc_with_parameter() argument
1652 return ci_send_msg_to_smc(rdev, msg); in ci_send_msg_to_smc_with_parameter()
1655 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev, in ci_send_msg_to_smc_return_parameter() argument
1660 smc_result = ci_send_msg_to_smc(rdev, msg); in ci_send_msg_to_smc_return_parameter()
1668 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n) in ci_dpm_force_state_sclk() argument
1670 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_sclk()
1674 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n); in ci_dpm_force_state_sclk()
1682 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n) in ci_dpm_force_state_mclk() argument
1684 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_mclk()
1688 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n); in ci_dpm_force_state_mclk()
1696 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n) in ci_dpm_force_state_pcie() argument
1698 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_pcie()
1702 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n); in ci_dpm_force_state_pcie()
1710 static int ci_set_power_limit(struct radeon_device *rdev, u32 n) in ci_set_power_limit() argument
1712 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_power_limit()
1716 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n); in ci_set_power_limit()
1724 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev, in ci_set_overdrive_target_tdp() argument
1728 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp); in ci_set_overdrive_target_tdp()
1735 static int ci_set_boot_state(struct radeon_device *rdev)
1737 return ci_enable_sclk_mclk_dpm(rdev, false);
1741 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev) in ci_get_average_sclk_freq() argument
1745 ci_send_msg_to_smc_return_parameter(rdev, in ci_get_average_sclk_freq()
1754 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev) in ci_get_average_mclk_freq() argument
1758 ci_send_msg_to_smc_return_parameter(rdev, in ci_get_average_mclk_freq()
1767 static void ci_dpm_start_smc(struct radeon_device *rdev) in ci_dpm_start_smc() argument
1771 ci_program_jump_on_start(rdev); in ci_dpm_start_smc()
1772 ci_start_smc_clock(rdev); in ci_dpm_start_smc()
1773 ci_start_smc(rdev); in ci_dpm_start_smc()
1774 for (i = 0; i < rdev->usec_timeout; i++) { in ci_dpm_start_smc()
1780 static void ci_dpm_stop_smc(struct radeon_device *rdev) in ci_dpm_stop_smc() argument
1782 ci_reset_smc(rdev); in ci_dpm_stop_smc()
1783 ci_stop_smc_clock(rdev); in ci_dpm_stop_smc()
1786 static int ci_process_firmware_header(struct radeon_device *rdev) in ci_process_firmware_header() argument
1788 struct ci_power_info *pi = ci_get_pi(rdev); in ci_process_firmware_header()
1792 ret = ci_read_smc_sram_dword(rdev, in ci_process_firmware_header()
1801 ret = ci_read_smc_sram_dword(rdev, in ci_process_firmware_header()
1810 ret = ci_read_smc_sram_dword(rdev, in ci_process_firmware_header()
1819 ret = ci_read_smc_sram_dword(rdev, in ci_process_firmware_header()
1828 ret = ci_read_smc_sram_dword(rdev, in ci_process_firmware_header()
1840 static void ci_read_clock_registers(struct radeon_device *rdev) in ci_read_clock_registers() argument
1842 struct ci_power_info *pi = ci_get_pi(rdev); in ci_read_clock_registers()
1867 static void ci_init_sclk_t(struct radeon_device *rdev) in ci_init_sclk_t() argument
1869 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_sclk_t()
1874 static void ci_enable_thermal_protection(struct radeon_device *rdev, in ci_enable_thermal_protection() argument
1886 static void ci_enable_acpi_power_management(struct radeon_device *rdev) in ci_enable_acpi_power_management() argument
1896 static int ci_enter_ulp_state(struct radeon_device *rdev)
1906 static int ci_exit_ulp_state(struct radeon_device *rdev)
1914 for (i = 0; i < rdev->usec_timeout; i++) {
1924 static int ci_notify_smc_display_change(struct radeon_device *rdev, in ci_notify_smc_display_change() argument
1929 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL; in ci_notify_smc_display_change()
1932 static int ci_enable_ds_master_switch(struct radeon_device *rdev, in ci_enable_ds_master_switch() argument
1935 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_ds_master_switch()
1939 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK) in ci_enable_ds_master_switch()
1942 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK) in ci_enable_ds_master_switch()
1947 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK) in ci_enable_ds_master_switch()
1955 static void ci_program_display_gap(struct radeon_device *rdev) in ci_program_display_gap() argument
1960 u32 ref_clock = rdev->clock.spll.reference_freq; in ci_program_display_gap()
1961 u32 refresh_rate = r600_dpm_get_vrefresh(rdev); in ci_program_display_gap()
1962 u32 vblank_time = r600_dpm_get_vblank_time(rdev); in ci_program_display_gap()
1965 if (rdev->pm.dpm.new_active_crtc_count > 0) in ci_program_display_gap()
1981 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64); in ci_program_display_gap()
1982 …ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - … in ci_program_display_gap()
1985 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1)); in ci_program_display_gap()
1989 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable) in ci_enable_spread_spectrum() argument
1991 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_spread_spectrum()
2011 static void ci_program_sstp(struct radeon_device *rdev) in ci_program_sstp() argument
2016 static void ci_enable_display_gap(struct radeon_device *rdev) in ci_enable_display_gap() argument
2027 static void ci_program_vc(struct radeon_device *rdev) in ci_program_vc() argument
2045 static void ci_clear_vc(struct radeon_device *rdev) in ci_clear_vc() argument
2063 static int ci_upload_firmware(struct radeon_device *rdev) in ci_upload_firmware() argument
2065 struct ci_power_info *pi = ci_get_pi(rdev); in ci_upload_firmware()
2068 for (i = 0; i < rdev->usec_timeout; i++) { in ci_upload_firmware()
2074 ci_stop_smc_clock(rdev); in ci_upload_firmware()
2075 ci_reset_smc(rdev); in ci_upload_firmware()
2077 ret = ci_load_smc_ucode(rdev, pi->sram_end); in ci_upload_firmware()
2083 static int ci_get_svi2_voltage_table(struct radeon_device *rdev, in ci_get_svi2_voltage_table() argument
2104 static int ci_construct_voltage_tables(struct radeon_device *rdev) in ci_construct_voltage_tables() argument
2106 struct ci_power_info *pi = ci_get_pi(rdev); in ci_construct_voltage_tables()
2110 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, in ci_construct_voltage_tables()
2116 ret = ci_get_svi2_voltage_table(rdev, in ci_construct_voltage_tables()
2117 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ci_construct_voltage_tables()
2124 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC, in ci_construct_voltage_tables()
2128 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, in ci_construct_voltage_tables()
2134 ret = ci_get_svi2_voltage_table(rdev, in ci_construct_voltage_tables()
2135 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ci_construct_voltage_tables()
2142 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI, in ci_construct_voltage_tables()
2146 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, in ci_construct_voltage_tables()
2152 ret = ci_get_svi2_voltage_table(rdev, in ci_construct_voltage_tables()
2153 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in ci_construct_voltage_tables()
2160 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD, in ci_construct_voltage_tables()
2166 static void ci_populate_smc_voltage_table(struct radeon_device *rdev, in ci_populate_smc_voltage_table() argument
2172 ret = ci_get_std_voltage_value_sidd(rdev, voltage_table, in ci_populate_smc_voltage_table()
2188 static int ci_populate_smc_vddc_table(struct radeon_device *rdev, in ci_populate_smc_vddc_table() argument
2191 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_vddc_table()
2196 ci_populate_smc_voltage_table(rdev, in ci_populate_smc_vddc_table()
2211 static int ci_populate_smc_vddci_table(struct radeon_device *rdev, in ci_populate_smc_vddci_table() argument
2215 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_vddci_table()
2219 ci_populate_smc_voltage_table(rdev, in ci_populate_smc_vddci_table()
2234 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev, in ci_populate_smc_mvdd_table() argument
2237 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_mvdd_table()
2242 ci_populate_smc_voltage_table(rdev, in ci_populate_smc_mvdd_table()
2257 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev, in ci_populate_smc_voltage_tables() argument
2262 ret = ci_populate_smc_vddc_table(rdev, table); in ci_populate_smc_voltage_tables()
2266 ret = ci_populate_smc_vddci_table(rdev, table); in ci_populate_smc_voltage_tables()
2270 ret = ci_populate_smc_mvdd_table(rdev, table); in ci_populate_smc_voltage_tables()
2277 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, in ci_populate_mvdd_value() argument
2280 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_mvdd_value()
2284 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) { in ci_populate_mvdd_value()
2285 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) { in ci_populate_mvdd_value()
2291 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count) in ci_populate_mvdd_value()
2298 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev, in ci_get_std_voltage_value_sidd() argument
2307 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in ci_get_std_voltage_value_sidd()
2310 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { in ci_get_std_voltage_value_sidd()
2311 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in ci_get_std_voltage_value_sidd()
2313 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2315 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in ci_get_std_voltage_value_sidd()
2318 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; in ci_get_std_voltage_value_sidd()
2320 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2322 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2328 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in ci_get_std_voltage_value_sidd()
2330 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2332 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in ci_get_std_voltage_value_sidd()
2335 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; in ci_get_std_voltage_value_sidd()
2337 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2339 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2349 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev, in ci_populate_phase_value_based_on_sclk() argument
2366 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev, in ci_populate_phase_value_based_on_mclk() argument
2383 static int ci_init_arb_table_index(struct radeon_device *rdev) in ci_init_arb_table_index() argument
2385 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_arb_table_index()
2389 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start, in ci_init_arb_table_index()
2397 return ci_write_smc_sram_dword(rdev, pi->arb_table_start, in ci_init_arb_table_index()
2401 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev, in ci_get_dependency_volt_by_clk() argument
2422 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev, in ci_get_sleep_divider_id_from_clock() argument
2442 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) in ci_initial_switch_from_arb_f0_to_f1() argument
2444 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); in ci_initial_switch_from_arb_f0_to_f1()
2447 static int ci_reset_to_default(struct radeon_device *rdev) in ci_reset_to_default() argument
2449 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? in ci_reset_to_default()
2453 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev) in ci_force_switch_to_arb_f0() argument
2462 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); in ci_force_switch_to_arb_f0()
2465 static void ci_register_patching_mc_arb(struct radeon_device *rdev, in ci_register_patching_mc_arb() argument
2477 ((rdev->pdev->device == 0x67B0) || in ci_register_patching_mc_arb()
2478 (rdev->pdev->device == 0x67B1))) { in ci_register_patching_mc_arb()
2492 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev, in ci_populate_memory_timing_parameters() argument
2501 radeon_atom_set_engine_dram_timings(rdev, sclk, mclk); in ci_populate_memory_timing_parameters()
2507 ci_register_patching_mc_arb(rdev, sclk, mclk, &dram_timing2); in ci_populate_memory_timing_parameters()
2516 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev) in ci_do_program_memory_timing_parameters() argument
2518 struct ci_power_info *pi = ci_get_pi(rdev); in ci_do_program_memory_timing_parameters()
2527 ret = ci_populate_memory_timing_parameters(rdev, in ci_do_program_memory_timing_parameters()
2537 ret = ci_copy_bytes_to_smc(rdev, in ci_do_program_memory_timing_parameters()
2546 static int ci_program_memory_timing_parameters(struct radeon_device *rdev) in ci_program_memory_timing_parameters() argument
2548 struct ci_power_info *pi = ci_get_pi(rdev); in ci_program_memory_timing_parameters()
2553 return ci_do_program_memory_timing_parameters(rdev); in ci_program_memory_timing_parameters()
2556 static void ci_populate_smc_initial_state(struct radeon_device *rdev, in ci_populate_smc_initial_state() argument
2560 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_initial_state()
2563 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) { in ci_populate_smc_initial_state()
2564 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= in ci_populate_smc_initial_state()
2571 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) { in ci_populate_smc_initial_state()
2572 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >= in ci_populate_smc_initial_state()
2596 static void ci_populate_smc_link_level(struct radeon_device *rdev, in ci_populate_smc_link_level() argument
2599 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_link_level()
2618 static int ci_populate_smc_uvd_level(struct radeon_device *rdev, in ci_populate_smc_uvd_level() argument
2626 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count; in ci_populate_smc_uvd_level()
2630 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk; in ci_populate_smc_uvd_level()
2632 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk; in ci_populate_smc_uvd_level()
2634 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_uvd_level()
2637 ret = radeon_atom_get_clock_dividers(rdev, in ci_populate_smc_uvd_level()
2645 ret = radeon_atom_get_clock_dividers(rdev, in ci_populate_smc_uvd_level()
2661 static int ci_populate_smc_vce_level(struct radeon_device *rdev, in ci_populate_smc_vce_level() argument
2669 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count; in ci_populate_smc_vce_level()
2673 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; in ci_populate_smc_vce_level()
2675 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_vce_level()
2678 ret = radeon_atom_get_clock_dividers(rdev, in ci_populate_smc_vce_level()
2694 static int ci_populate_smc_acp_level(struct radeon_device *rdev, in ci_populate_smc_acp_level() argument
2702 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count); in ci_populate_smc_acp_level()
2706 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk; in ci_populate_smc_acp_level()
2708 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v; in ci_populate_smc_acp_level()
2711 ret = radeon_atom_get_clock_dividers(rdev, in ci_populate_smc_acp_level()
2726 static int ci_populate_smc_samu_level(struct radeon_device *rdev, in ci_populate_smc_samu_level() argument
2734 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count; in ci_populate_smc_samu_level()
2738 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk; in ci_populate_smc_samu_level()
2740 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_samu_level()
2743 ret = radeon_atom_get_clock_dividers(rdev, in ci_populate_smc_samu_level()
2758 static int ci_calculate_mclk_params(struct radeon_device *rdev, in ci_calculate_mclk_params() argument
2764 struct ci_power_info *pi = ci_get_pi(rdev); in ci_calculate_mclk_params()
2777 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); in ci_calculate_mclk_params()
2801 u32 reference_clock = rdev->clock.mpll.reference_freq; in ci_calculate_mclk_params()
2810 if (radeon_atombios_get_asic_ss_info(rdev, &ss, in ci_calculate_mclk_params()
2845 static int ci_populate_single_memory_level(struct radeon_device *rdev, in ci_populate_single_memory_level() argument
2849 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_single_memory_level()
2853 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2854 ret = ci_get_dependency_volt_by_clk(rdev, in ci_populate_single_memory_level()
2855 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ci_populate_single_memory_level()
2861 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2862 ret = ci_get_dependency_volt_by_clk(rdev, in ci_populate_single_memory_level()
2863 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ci_populate_single_memory_level()
2869 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2870 ret = ci_get_dependency_volt_by_clk(rdev, in ci_populate_single_memory_level()
2871 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in ci_populate_single_memory_level()
2880 ci_populate_phase_value_based_on_mclk(rdev, in ci_populate_single_memory_level()
2881 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in ci_populate_single_memory_level()
2903 (rdev->pm.dpm.new_active_crtc_count <= 2)) in ci_populate_single_memory_level()
2935 …ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_s… in ci_populate_single_memory_level()
2959 static int ci_populate_smc_acpi_level(struct radeon_device *rdev, in ci_populate_smc_acpi_level() argument
2962 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_acpi_level()
2980 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq; in ci_populate_smc_acpi_level()
2982 ret = radeon_atom_get_clock_dividers(rdev, in ci_populate_smc_acpi_level()
3031 if (ci_populate_mvdd_value(rdev, 0, &voltage_level)) in ci_populate_smc_acpi_level()
3075 static int ci_enable_ulv(struct radeon_device *rdev, bool enable) in ci_enable_ulv() argument
3077 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_ulv()
3082 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? in ci_enable_ulv()
3085 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? in ci_enable_ulv()
3092 static int ci_populate_ulv_level(struct radeon_device *rdev, in ci_populate_ulv_level() argument
3095 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_ulv_level()
3096 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time; in ci_populate_ulv_level()
3107 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) in ci_populate_ulv_level()
3111 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; in ci_populate_ulv_level()
3113 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) in ci_populate_ulv_level()
3117 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) * in ci_populate_ulv_level()
3129 static int ci_calculate_sclk_params(struct radeon_device *rdev, in ci_calculate_sclk_params() argument
3133 struct ci_power_info *pi = ci_get_pi(rdev); in ci_calculate_sclk_params()
3139 u32 reference_clock = rdev->clock.spll.reference_freq; in ci_calculate_sclk_params()
3144 ret = radeon_atom_get_clock_dividers(rdev, in ci_calculate_sclk_params()
3161 if (radeon_atombios_get_asic_ss_info(rdev, &ss, in ci_calculate_sclk_params()
3185 static int ci_populate_single_graphic_level(struct radeon_device *rdev, in ci_populate_single_graphic_level() argument
3190 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_single_graphic_level()
3193 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level); in ci_populate_single_graphic_level()
3197 ret = ci_get_dependency_volt_by_clk(rdev, in ci_populate_single_graphic_level()
3198 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in ci_populate_single_graphic_level()
3209 ci_populate_phase_value_based_on_sclk(rdev, in ci_populate_single_graphic_level()
3210 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in ci_populate_single_graphic_level()
3225 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev, in ci_populate_single_graphic_level()
3246 static int ci_populate_all_graphic_levels(struct radeon_device *rdev) in ci_populate_all_graphic_levels() argument
3248 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_all_graphic_levels()
3260 ret = ci_populate_single_graphic_level(rdev, in ci_populate_all_graphic_levels()
3278 ret = ci_copy_bytes_to_smc(rdev, level_array_address, in ci_populate_all_graphic_levels()
3287 static int ci_populate_ulv_state(struct radeon_device *rdev, in ci_populate_ulv_state() argument
3290 return ci_populate_ulv_level(rdev, ulv_level); in ci_populate_ulv_state()
3293 static int ci_populate_all_memory_levels(struct radeon_device *rdev) in ci_populate_all_memory_levels() argument
3295 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_all_memory_levels()
3309 ret = ci_populate_single_memory_level(rdev, in ci_populate_all_memory_levels()
3319 ((rdev->pdev->device == 0x67B0) || (rdev->pdev->device == 0x67B1))) { in ci_populate_all_memory_levels()
3335 ret = ci_copy_bytes_to_smc(rdev, level_array_address, in ci_populate_all_memory_levels()
3344 static void ci_reset_single_dpm_table(struct radeon_device *rdev, in ci_reset_single_dpm_table() argument
3363 static int ci_setup_default_pcie_tables(struct radeon_device *rdev) in ci_setup_default_pcie_tables() argument
3365 struct ci_power_info *pi = ci_get_pi(rdev); in ci_setup_default_pcie_tables()
3378 ci_reset_single_dpm_table(rdev, in ci_setup_default_pcie_tables()
3382 if (rdev->family == CHIP_BONAIRE) in ci_setup_default_pcie_tables()
3411 static int ci_setup_default_dpm_tables(struct radeon_device *rdev) in ci_setup_default_dpm_tables() argument
3413 struct ci_power_info *pi = ci_get_pi(rdev); in ci_setup_default_dpm_tables()
3415 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_setup_default_dpm_tables()
3417 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_setup_default_dpm_tables()
3419 &rdev->pm.dpm.dyn_state.cac_leakage_table; in ci_setup_default_dpm_tables()
3433 ci_reset_single_dpm_table(rdev, in ci_setup_default_dpm_tables()
3436 ci_reset_single_dpm_table(rdev, in ci_setup_default_dpm_tables()
3439 ci_reset_single_dpm_table(rdev, in ci_setup_default_dpm_tables()
3442 ci_reset_single_dpm_table(rdev, in ci_setup_default_dpm_tables()
3445 ci_reset_single_dpm_table(rdev, in ci_setup_default_dpm_tables()
3484 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; in ci_setup_default_dpm_tables()
3494 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk; in ci_setup_default_dpm_tables()
3504 ci_setup_default_pcie_tables(rdev); in ci_setup_default_dpm_tables()
3525 static int ci_init_smc_table(struct radeon_device *rdev) in ci_init_smc_table() argument
3527 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_smc_table()
3529 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; in ci_init_smc_table()
3533 ret = ci_setup_default_dpm_tables(rdev); in ci_init_smc_table()
3538 ci_populate_smc_voltage_tables(rdev, table); in ci_init_smc_table()
3540 ci_init_fps_limits(rdev); in ci_init_smc_table()
3542 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) in ci_init_smc_table()
3545 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in ci_init_smc_table()
3552 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv); in ci_init_smc_table()
3558 ret = ci_populate_all_graphic_levels(rdev); in ci_init_smc_table()
3562 ret = ci_populate_all_memory_levels(rdev); in ci_init_smc_table()
3566 ci_populate_smc_link_level(rdev, table); in ci_init_smc_table()
3568 ret = ci_populate_smc_acpi_level(rdev, table); in ci_init_smc_table()
3572 ret = ci_populate_smc_vce_level(rdev, table); in ci_init_smc_table()
3576 ret = ci_populate_smc_acp_level(rdev, table); in ci_init_smc_table()
3580 ret = ci_populate_smc_samu_level(rdev, table); in ci_init_smc_table()
3584 ret = ci_do_program_memory_timing_parameters(rdev); in ci_init_smc_table()
3588 ret = ci_populate_smc_uvd_level(rdev, table); in ci_init_smc_table()
3611 ci_populate_smc_initial_state(rdev, radeon_boot_state); in ci_init_smc_table()
3613 ret = ci_populate_bapm_parameters_in_dpm_table(rdev); in ci_init_smc_table()
3661 ret = ci_copy_bytes_to_smc(rdev, in ci_init_smc_table()
3673 static void ci_trim_single_dpm_states(struct radeon_device *rdev, in ci_trim_single_dpm_states() argument
3688 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev, in ci_trim_pcie_dpm_states() argument
3692 struct ci_power_info *pi = ci_get_pi(rdev); in ci_trim_pcie_dpm_states()
3719 static int ci_trim_dpm_states(struct radeon_device *rdev, in ci_trim_dpm_states() argument
3723 struct ci_power_info *pi = ci_get_pi(rdev); in ci_trim_dpm_states()
3734 ci_trim_single_dpm_states(rdev, in ci_trim_dpm_states()
3739 ci_trim_single_dpm_states(rdev, in ci_trim_dpm_states()
3744 ci_trim_pcie_dpm_states(rdev, in ci_trim_dpm_states()
3753 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev) in ci_apply_disp_minimum_voltage_request() argument
3756 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk; in ci_apply_disp_minimum_voltage_request()
3758 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_apply_disp_minimum_voltage_request()
3768 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk) in ci_apply_disp_minimum_voltage_request()
3775 return (ci_send_msg_to_smc_with_parameter(rdev, in ci_apply_disp_minimum_voltage_request()
3785 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev) in ci_upload_dpm_level_enable_mask() argument
3787 struct ci_power_info *pi = ci_get_pi(rdev); in ci_upload_dpm_level_enable_mask()
3790 ci_apply_disp_minimum_voltage_request(rdev); in ci_upload_dpm_level_enable_mask()
3794 result = ci_send_msg_to_smc_with_parameter(rdev, in ci_upload_dpm_level_enable_mask()
3804 result = ci_send_msg_to_smc_with_parameter(rdev, in ci_upload_dpm_level_enable_mask()
3814 result = ci_send_msg_to_smc_with_parameter(rdev, in ci_upload_dpm_level_enable_mask()
3825 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev, in ci_find_dpm_states_clocks_in_dpm_table() argument
3828 struct ci_power_info *pi = ci_get_pi(rdev); in ci_find_dpm_states_clocks_in_dpm_table()
3859 if (rdev->pm.dpm.current_active_crtc_count != in ci_find_dpm_states_clocks_in_dpm_table()
3860 rdev->pm.dpm.new_active_crtc_count) in ci_find_dpm_states_clocks_in_dpm_table()
3864 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev, in ci_populate_and_upload_sclk_mclk_dpm_levels() argument
3867 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_and_upload_sclk_mclk_dpm_levels()
3884 ret = ci_populate_all_graphic_levels(rdev); in ci_populate_and_upload_sclk_mclk_dpm_levels()
3890 ret = ci_populate_all_memory_levels(rdev); in ci_populate_and_upload_sclk_mclk_dpm_levels()
3898 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable) in ci_enable_uvd_dpm() argument
3900 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_uvd_dpm()
3904 if (rdev->pm.dpm.ac_power) in ci_enable_uvd_dpm()
3905 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_enable_uvd_dpm()
3907 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_enable_uvd_dpm()
3912 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) { in ci_enable_uvd_dpm()
3913 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { in ci_enable_uvd_dpm()
3921 ci_send_msg_to_smc_with_parameter(rdev, in ci_enable_uvd_dpm()
3928 ci_send_msg_to_smc_with_parameter(rdev, in ci_enable_uvd_dpm()
3936 ci_send_msg_to_smc_with_parameter(rdev, in ci_enable_uvd_dpm()
3942 return (ci_send_msg_to_smc(rdev, enable ? in ci_enable_uvd_dpm()
3947 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable) in ci_enable_vce_dpm() argument
3949 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_vce_dpm()
3953 if (rdev->pm.dpm.ac_power) in ci_enable_vce_dpm()
3954 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_enable_vce_dpm()
3956 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_enable_vce_dpm()
3960 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) { in ci_enable_vce_dpm()
3961 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { in ci_enable_vce_dpm()
3969 ci_send_msg_to_smc_with_parameter(rdev, in ci_enable_vce_dpm()
3974 return (ci_send_msg_to_smc(rdev, enable ? in ci_enable_vce_dpm()
3980 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
3982 struct ci_power_info *pi = ci_get_pi(rdev);
3986 if (rdev->pm.dpm.ac_power)
3987 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3989 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3993 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3994 … if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4002 ci_send_msg_to_smc_with_parameter(rdev,
4006 return (ci_send_msg_to_smc(rdev, enable ?
4011 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
4013 struct ci_power_info *pi = ci_get_pi(rdev);
4017 if (rdev->pm.dpm.ac_power)
4018 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4020 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4024 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4025 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4033 ci_send_msg_to_smc_with_parameter(rdev,
4038 return (ci_send_msg_to_smc(rdev, enable ?
4044 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate) in ci_update_uvd_dpm() argument
4046 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_uvd_dpm()
4051 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) in ci_update_uvd_dpm()
4055 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; in ci_update_uvd_dpm()
4063 return ci_enable_uvd_dpm(rdev, !gate); in ci_update_uvd_dpm()
4066 static u8 ci_get_vce_boot_level(struct radeon_device *rdev) in ci_get_vce_boot_level() argument
4071 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in ci_get_vce_boot_level()
4081 static int ci_update_vce_dpm(struct radeon_device *rdev, in ci_update_vce_dpm() argument
4085 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_vce_dpm()
4092 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false); in ci_update_vce_dpm()
4094 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); in ci_update_vce_dpm()
4100 ret = ci_enable_vce_dpm(rdev, true); in ci_update_vce_dpm()
4103 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true); in ci_update_vce_dpm()
4105 ret = ci_enable_vce_dpm(rdev, false); in ci_update_vce_dpm()
4112 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
4114 return ci_enable_samu_dpm(rdev, gate);
4117 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
4119 struct ci_power_info *pi = ci_get_pi(rdev);
4131 return ci_enable_acp_dpm(rdev, !gate);
4135 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev, in ci_generate_dpm_level_enable_mask() argument
4138 struct ci_power_info *pi = ci_get_pi(rdev); in ci_generate_dpm_level_enable_mask()
4141 ret = ci_trim_dpm_states(rdev, radeon_state); in ci_generate_dpm_level_enable_mask()
4161 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev, in ci_get_lowest_enabled_level() argument
4173 int ci_dpm_force_performance_level(struct radeon_device *rdev, in ci_dpm_force_performance_level() argument
4176 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_performance_level()
4188 ret = ci_dpm_force_state_pcie(rdev, level); in ci_dpm_force_performance_level()
4191 for (i = 0; i < rdev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4207 ret = ci_dpm_force_state_sclk(rdev, levels); in ci_dpm_force_performance_level()
4210 for (i = 0; i < rdev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4226 ret = ci_dpm_force_state_mclk(rdev, levels); in ci_dpm_force_performance_level()
4229 for (i = 0; i < rdev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4241 levels = ci_get_lowest_enabled_level(rdev, in ci_dpm_force_performance_level()
4243 ret = ci_dpm_force_state_sclk(rdev, levels); in ci_dpm_force_performance_level()
4246 for (i = 0; i < rdev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4256 levels = ci_get_lowest_enabled_level(rdev, in ci_dpm_force_performance_level()
4258 ret = ci_dpm_force_state_mclk(rdev, levels); in ci_dpm_force_performance_level()
4261 for (i = 0; i < rdev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4271 levels = ci_get_lowest_enabled_level(rdev, in ci_dpm_force_performance_level()
4273 ret = ci_dpm_force_state_pcie(rdev, levels); in ci_dpm_force_performance_level()
4276 for (i = 0; i < rdev->usec_timeout; i++) { in ci_dpm_force_performance_level()
4288 smc_result = ci_send_msg_to_smc(rdev, in ci_dpm_force_performance_level()
4293 ret = ci_upload_dpm_level_enable_mask(rdev); in ci_dpm_force_performance_level()
4298 rdev->pm.dpm.forced_level = level; in ci_dpm_force_performance_level()
4303 static int ci_set_mc_special_registers(struct radeon_device *rdev, in ci_set_mc_special_registers() argument
4306 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_mc_special_registers()
4501 static int ci_register_patching_mc_seq(struct radeon_device *rdev, in ci_register_patching_mc_seq() argument
4512 ((rdev->pdev->device == 0x67B0) || in ci_register_patching_mc_seq()
4513 (rdev->pdev->device == 0x67B1))) { in ci_register_patching_mc_seq()
4591 static int ci_initialize_mc_reg_table(struct radeon_device *rdev) in ci_initialize_mc_reg_table() argument
4593 struct ci_power_info *pi = ci_get_pi(rdev); in ci_initialize_mc_reg_table()
4596 u8 module_index = rv770_get_memory_module_index(rdev); in ci_initialize_mc_reg_table()
4624 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); in ci_initialize_mc_reg_table()
4634 ret = ci_register_patching_mc_seq(rdev, ci_table); in ci_initialize_mc_reg_table()
4638 ret = ci_set_mc_special_registers(rdev, ci_table); in ci_initialize_mc_reg_table()
4650 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev, in ci_populate_mc_reg_addresses() argument
4653 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_mc_reg_addresses()
4685 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, in ci_convert_mc_reg_table_entry_to_smc() argument
4689 struct ci_power_info *pi = ci_get_pi(rdev); in ci_convert_mc_reg_table_entry_to_smc()
4705 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev, in ci_convert_mc_reg_table_to_smc() argument
4708 struct ci_power_info *pi = ci_get_pi(rdev); in ci_convert_mc_reg_table_to_smc()
4712 ci_convert_mc_reg_table_entry_to_smc(rdev, in ci_convert_mc_reg_table_to_smc()
4717 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev) in ci_populate_initial_mc_reg_table() argument
4719 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_initial_mc_reg_table()
4724 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4727 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4729 return ci_copy_bytes_to_smc(rdev, in ci_populate_initial_mc_reg_table()
4736 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev) in ci_update_and_upload_mc_reg_table() argument
4738 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_and_upload_mc_reg_table()
4745 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); in ci_update_and_upload_mc_reg_table()
4747 return ci_copy_bytes_to_smc(rdev, in ci_update_and_upload_mc_reg_table()
4756 static void ci_enable_voltage_control(struct radeon_device *rdev) in ci_enable_voltage_control() argument
4764 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev, in ci_get_maximum_link_speed() argument
4780 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev) in ci_get_current_pcie_speed() argument
4790 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev) in ci_get_current_pcie_lane_number() argument
4816 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev, in ci_request_link_speed_change_before_state_change() argument
4820 struct ci_power_info *pi = ci_get_pi(rdev); in ci_request_link_speed_change_before_state_change()
4822 ci_get_maximum_link_speed(rdev, radeon_new_state); in ci_request_link_speed_change_before_state_change()
4826 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state); in ci_request_link_speed_change_before_state_change()
4836 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) in ci_request_link_speed_change_before_state_change()
4842 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) in ci_request_link_speed_change_before_state_change()
4846 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev); in ci_request_link_speed_change_before_state_change()
4855 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev, in ci_notify_link_speed_change_after_state_change() argument
4859 struct ci_power_info *pi = ci_get_pi(rdev); in ci_notify_link_speed_change_after_state_change()
4861 ci_get_maximum_link_speed(rdev, radeon_new_state); in ci_notify_link_speed_change_after_state_change()
4873 (ci_get_current_pcie_speed(rdev) > 0)) in ci_notify_link_speed_change_after_state_change()
4877 radeon_acpi_pcie_performance_request(rdev, request, false); in ci_notify_link_speed_change_after_state_change()
4882 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev) in ci_set_private_data_variables_based_on_pptable() argument
4884 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_private_data_variables_based_on_pptable()
4886 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_set_private_data_variables_based_on_pptable()
4888 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_set_private_data_variables_based_on_pptable()
4890 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; in ci_set_private_data_variables_based_on_pptable()
4913 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = in ci_set_private_data_variables_based_on_pptable()
4915 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = in ci_set_private_data_variables_based_on_pptable()
4917 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = in ci_set_private_data_variables_based_on_pptable()
4919 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = in ci_set_private_data_variables_based_on_pptable()
4925 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc) in ci_patch_with_vddc_leakage() argument
4927 struct ci_power_info *pi = ci_get_pi(rdev); in ci_patch_with_vddc_leakage()
4939 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci) in ci_patch_with_vddci_leakage() argument
4941 struct ci_power_info *pi = ci_get_pi(rdev); in ci_patch_with_vddci_leakage()
4953 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, in ci_patch_clock_voltage_dependency_table_with_vddc_leakage() argument
4960 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); in ci_patch_clock_voltage_dependency_table_with_vddc_leakage()
4964 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev, in ci_patch_clock_voltage_dependency_table_with_vddci_leakage() argument
4971 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v); in ci_patch_clock_voltage_dependency_table_with_vddci_leakage()
4975 …atic void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage() argument
4982 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); in ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage()
4986 …atic void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev, in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage() argument
4993 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v); in ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage()
4997 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev, in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage() argument
5004 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage); in ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage()
5008 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev, in ci_patch_clock_voltage_limits_with_vddc_leakage() argument
5012 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc); in ci_patch_clock_voltage_limits_with_vddc_leakage()
5013 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci); in ci_patch_clock_voltage_limits_with_vddc_leakage()
5017 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev, in ci_patch_cac_leakage_table_with_vddc_leakage() argument
5024 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc); in ci_patch_cac_leakage_table_with_vddc_leakage()
5028 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev) in ci_patch_dependency_tables_with_leakage() argument
5031 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, in ci_patch_dependency_tables_with_leakage()
5032 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in ci_patch_dependency_tables_with_leakage()
5033 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, in ci_patch_dependency_tables_with_leakage()
5034 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in ci_patch_dependency_tables_with_leakage()
5035 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, in ci_patch_dependency_tables_with_leakage()
5036 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk); in ci_patch_dependency_tables_with_leakage()
5037 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev, in ci_patch_dependency_tables_with_leakage()
5038 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); in ci_patch_dependency_tables_with_leakage()
5039 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev, in ci_patch_dependency_tables_with_leakage()
5040 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5041 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev, in ci_patch_dependency_tables_with_leakage()
5042 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5043 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, in ci_patch_dependency_tables_with_leakage()
5044 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5045 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev, in ci_patch_dependency_tables_with_leakage()
5046 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5047 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev, in ci_patch_dependency_tables_with_leakage()
5048 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table); in ci_patch_dependency_tables_with_leakage()
5049 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev, in ci_patch_dependency_tables_with_leakage()
5050 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac); in ci_patch_dependency_tables_with_leakage()
5051 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev, in ci_patch_dependency_tables_with_leakage()
5052 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc); in ci_patch_dependency_tables_with_leakage()
5053 ci_patch_cac_leakage_table_with_vddc_leakage(rdev, in ci_patch_dependency_tables_with_leakage()
5054 &rdev->pm.dpm.dyn_state.cac_leakage_table); in ci_patch_dependency_tables_with_leakage()
5058 static void ci_get_memory_type(struct radeon_device *rdev) in ci_get_memory_type() argument
5060 struct ci_power_info *pi = ci_get_pi(rdev); in ci_get_memory_type()
5073 static void ci_update_current_ps(struct radeon_device *rdev, in ci_update_current_ps() argument
5077 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_current_ps()
5084 static void ci_update_requested_ps(struct radeon_device *rdev, in ci_update_requested_ps() argument
5088 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_requested_ps()
5095 int ci_dpm_pre_set_power_state(struct radeon_device *rdev) in ci_dpm_pre_set_power_state() argument
5097 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_pre_set_power_state()
5098 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; in ci_dpm_pre_set_power_state()
5101 ci_update_requested_ps(rdev, new_ps); in ci_dpm_pre_set_power_state()
5103 ci_apply_state_adjust_rules(rdev, &pi->requested_rps); in ci_dpm_pre_set_power_state()
5108 void ci_dpm_post_set_power_state(struct radeon_device *rdev) in ci_dpm_post_set_power_state() argument
5110 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_post_set_power_state()
5113 ci_update_current_ps(rdev, new_ps); in ci_dpm_post_set_power_state()
5117 void ci_dpm_setup_asic(struct radeon_device *rdev) in ci_dpm_setup_asic() argument
5121 r = ci_mc_load_microcode(rdev); in ci_dpm_setup_asic()
5124 ci_read_clock_registers(rdev); in ci_dpm_setup_asic()
5125 ci_get_memory_type(rdev); in ci_dpm_setup_asic()
5126 ci_enable_acpi_power_management(rdev); in ci_dpm_setup_asic()
5127 ci_init_sclk_t(rdev); in ci_dpm_setup_asic()
5130 int ci_dpm_enable(struct radeon_device *rdev) in ci_dpm_enable() argument
5132 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_enable()
5133 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in ci_dpm_enable()
5136 if (ci_is_smc_running(rdev)) in ci_dpm_enable()
5139 ci_enable_voltage_control(rdev); in ci_dpm_enable()
5140 ret = ci_construct_voltage_tables(rdev); in ci_dpm_enable()
5147 ret = ci_initialize_mc_reg_table(rdev); in ci_dpm_enable()
5152 ci_enable_spread_spectrum(rdev, true); in ci_dpm_enable()
5154 ci_enable_thermal_protection(rdev, true); in ci_dpm_enable()
5155 ci_program_sstp(rdev); in ci_dpm_enable()
5156 ci_enable_display_gap(rdev); in ci_dpm_enable()
5157 ci_program_vc(rdev); in ci_dpm_enable()
5158 ret = ci_upload_firmware(rdev); in ci_dpm_enable()
5163 ret = ci_process_firmware_header(rdev); in ci_dpm_enable()
5168 ret = ci_initial_switch_from_arb_f0_to_f1(rdev); in ci_dpm_enable()
5173 ret = ci_init_smc_table(rdev); in ci_dpm_enable()
5178 ret = ci_init_arb_table_index(rdev); in ci_dpm_enable()
5184 ret = ci_populate_initial_mc_reg_table(rdev); in ci_dpm_enable()
5190 ret = ci_populate_pm_base(rdev); in ci_dpm_enable()
5195 ci_dpm_start_smc(rdev); in ci_dpm_enable()
5196 ci_enable_vr_hot_gpio_interrupt(rdev); in ci_dpm_enable()
5197 ret = ci_notify_smc_display_change(rdev, false); in ci_dpm_enable()
5202 ci_enable_sclk_control(rdev, true); in ci_dpm_enable()
5203 ret = ci_enable_ulv(rdev, true); in ci_dpm_enable()
5208 ret = ci_enable_ds_master_switch(rdev, true); in ci_dpm_enable()
5213 ret = ci_start_dpm(rdev); in ci_dpm_enable()
5218 ret = ci_enable_didt(rdev, true); in ci_dpm_enable()
5223 ret = ci_enable_smc_cac(rdev, true); in ci_dpm_enable()
5228 ret = ci_enable_power_containment(rdev, true); in ci_dpm_enable()
5234 ret = ci_power_control_set_level(rdev); in ci_dpm_enable()
5240 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); in ci_dpm_enable()
5242 ret = ci_enable_thermal_based_sclk_dpm(rdev, true); in ci_dpm_enable()
5248 ci_thermal_start_thermal_controller(rdev); in ci_dpm_enable()
5250 ci_update_current_ps(rdev, boot_ps); in ci_dpm_enable()
5255 static int ci_set_temperature_range(struct radeon_device *rdev) in ci_set_temperature_range() argument
5259 ret = ci_thermal_enable_alert(rdev, false); in ci_set_temperature_range()
5262 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); in ci_set_temperature_range()
5265 ret = ci_thermal_enable_alert(rdev, true); in ci_set_temperature_range()
5272 int ci_dpm_late_enable(struct radeon_device *rdev) in ci_dpm_late_enable() argument
5276 ret = ci_set_temperature_range(rdev); in ci_dpm_late_enable()
5280 ci_dpm_powergate_uvd(rdev, true); in ci_dpm_late_enable()
5285 void ci_dpm_disable(struct radeon_device *rdev) in ci_dpm_disable() argument
5287 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_disable()
5288 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in ci_dpm_disable()
5290 ci_dpm_powergate_uvd(rdev, false); in ci_dpm_disable()
5292 if (!ci_is_smc_running(rdev)) in ci_dpm_disable()
5295 ci_thermal_stop_thermal_controller(rdev); in ci_dpm_disable()
5298 ci_enable_thermal_protection(rdev, false); in ci_dpm_disable()
5299 ci_enable_power_containment(rdev, false); in ci_dpm_disable()
5300 ci_enable_smc_cac(rdev, false); in ci_dpm_disable()
5301 ci_enable_didt(rdev, false); in ci_dpm_disable()
5302 ci_enable_spread_spectrum(rdev, false); in ci_dpm_disable()
5303 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); in ci_dpm_disable()
5304 ci_stop_dpm(rdev); in ci_dpm_disable()
5305 ci_enable_ds_master_switch(rdev, false); in ci_dpm_disable()
5306 ci_enable_ulv(rdev, false); in ci_dpm_disable()
5307 ci_clear_vc(rdev); in ci_dpm_disable()
5308 ci_reset_to_default(rdev); in ci_dpm_disable()
5309 ci_dpm_stop_smc(rdev); in ci_dpm_disable()
5310 ci_force_switch_to_arb_f0(rdev); in ci_dpm_disable()
5311 ci_enable_thermal_based_sclk_dpm(rdev, false); in ci_dpm_disable()
5313 ci_update_current_ps(rdev, boot_ps); in ci_dpm_disable()
5316 int ci_dpm_set_power_state(struct radeon_device *rdev) in ci_dpm_set_power_state() argument
5318 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_set_power_state()
5323 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps); in ci_dpm_set_power_state()
5325 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); in ci_dpm_set_power_state()
5326 ret = ci_freeze_sclk_mclk_dpm(rdev); in ci_dpm_set_power_state()
5331 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps); in ci_dpm_set_power_state()
5336 ret = ci_generate_dpm_level_enable_mask(rdev, new_ps); in ci_dpm_set_power_state()
5342 ret = ci_update_vce_dpm(rdev, new_ps, old_ps); in ci_dpm_set_power_state()
5348 ret = ci_update_sclk_t(rdev); in ci_dpm_set_power_state()
5354 ret = ci_update_and_upload_mc_reg_table(rdev); in ci_dpm_set_power_state()
5360 ret = ci_program_memory_timing_parameters(rdev); in ci_dpm_set_power_state()
5365 ret = ci_unfreeze_sclk_mclk_dpm(rdev); in ci_dpm_set_power_state()
5370 ret = ci_upload_dpm_level_enable_mask(rdev); in ci_dpm_set_power_state()
5376 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); in ci_dpm_set_power_state()
5382 void ci_dpm_reset_asic(struct radeon_device *rdev)
5384 ci_set_boot_state(rdev);
5388 void ci_dpm_display_configuration_changed(struct radeon_device *rdev) in ci_dpm_display_configuration_changed() argument
5390 ci_program_display_gap(rdev); in ci_dpm_display_configuration_changed()
5416 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev, in ci_parse_pplib_non_clock_info() argument
5434 rdev->pm.dpm.boot_ps = rps; in ci_parse_pplib_non_clock_info()
5436 rdev->pm.dpm.uvd_ps = rps; in ci_parse_pplib_non_clock_info()
5439 static void ci_parse_pplib_clock_info(struct radeon_device *rdev, in ci_parse_pplib_clock_info() argument
5443 struct ci_power_info *pi = ci_get_pi(rdev); in ci_parse_pplib_clock_info()
5454 pl->pcie_gen = r600_get_pcie_gen_support(rdev, in ci_parse_pplib_clock_info()
5458 pl->pcie_lane = r600_get_pcie_lane_support(rdev, in ci_parse_pplib_clock_info()
5508 static int ci_parse_power_table(struct radeon_device *rdev) in ci_parse_power_table() argument
5510 struct radeon_mode_info *mode_info = &rdev->mode_info; in ci_parse_power_table()
5540 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * in ci_parse_power_table()
5542 if (!rdev->pm.dpm.ps) in ci_parse_power_table()
5551 if (!rdev->pm.power_state[i].clock_info) in ci_parse_power_table()
5555 kfree(rdev->pm.dpm.ps); in ci_parse_power_table()
5558 rdev->pm.dpm.ps[i].ps_priv = ps; in ci_parse_power_table()
5559 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], in ci_parse_power_table()
5573 ci_parse_pplib_clock_info(rdev, in ci_parse_power_table()
5574 &rdev->pm.dpm.ps[i], k, in ci_parse_power_table()
5580 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in ci_parse_power_table()
5585 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; in ci_parse_power_table()
5592 rdev->pm.dpm.vce_states[i].sclk = sclk; in ci_parse_power_table()
5593 rdev->pm.dpm.vce_states[i].mclk = mclk; in ci_parse_power_table()
5599 static int ci_get_vbios_boot_values(struct radeon_device *rdev, in ci_get_vbios_boot_values() argument
5602 struct radeon_mode_info *mode_info = &rdev->mode_info; in ci_get_vbios_boot_values()
5616 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev); in ci_get_vbios_boot_values()
5617 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev); in ci_get_vbios_boot_values()
5626 void ci_dpm_fini(struct radeon_device *rdev) in ci_dpm_fini() argument
5630 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in ci_dpm_fini()
5631 kfree(rdev->pm.dpm.ps[i].ps_priv); in ci_dpm_fini()
5633 kfree(rdev->pm.dpm.ps); in ci_dpm_fini()
5634 kfree(rdev->pm.dpm.priv); in ci_dpm_fini()
5635 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); in ci_dpm_fini()
5636 r600_free_extended_power_table(rdev); in ci_dpm_fini()
5639 int ci_dpm_init(struct radeon_device *rdev) in ci_dpm_init() argument
5653 rdev->pm.dpm.priv = pi; in ci_dpm_init()
5655 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); in ci_dpm_init()
5672 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state); in ci_dpm_init()
5674 ci_dpm_fini(rdev); in ci_dpm_init()
5678 ret = r600_get_platform_caps(rdev); in ci_dpm_init()
5680 ci_dpm_fini(rdev); in ci_dpm_init()
5684 ret = r600_parse_extended_power_table(rdev); in ci_dpm_init()
5686 ci_dpm_fini(rdev); in ci_dpm_init()
5690 ret = ci_parse_power_table(rdev); in ci_dpm_init()
5692 ci_dpm_fini(rdev); in ci_dpm_init()
5716 if ((rdev->pdev->device == 0x6658) && in ci_dpm_init()
5717 (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) { in ci_dpm_init()
5728 ci_initialize_powertune_defaults(rdev); in ci_dpm_init()
5737 ci_get_leakage_voltages(rdev); in ci_dpm_init()
5738 ci_patch_dependency_tables_with_leakage(rdev); in ci_dpm_init()
5739 ci_set_private_data_variables_based_on_pptable(rdev); in ci_dpm_init()
5741 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = in ci_dpm_init()
5743 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { in ci_dpm_init()
5744 ci_dpm_fini(rdev); in ci_dpm_init()
5747 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; in ci_dpm_init()
5748 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; in ci_dpm_init()
5749 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; in ci_dpm_init()
5750 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; in ci_dpm_init()
5751 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; in ci_dpm_init()
5752 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; in ci_dpm_init()
5753 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; in ci_dpm_init()
5754 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; in ci_dpm_init()
5755 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; in ci_dpm_init()
5757 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in ci_dpm_init()
5758 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in ci_dpm_init()
5759 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in ci_dpm_init()
5761 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in ci_dpm_init()
5762 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; in ci_dpm_init()
5763 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in ci_dpm_init()
5764 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; in ci_dpm_init()
5766 if (rdev->family == CHIP_HAWAII) { in ci_dpm_init()
5780 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_VRHOT_GPIO_PINID); in ci_dpm_init()
5783 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; in ci_dpm_init()
5786 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; in ci_dpm_init()
5789 gpio = radeon_atombios_lookup_gpio(rdev, PP_AC_DC_SWITCH_GPIO_PINID); in ci_dpm_init()
5792 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC; in ci_dpm_init()
5795 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC; in ci_dpm_init()
5798 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_PCC_GPIO_PINID); in ci_dpm_init()
5830 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT)) in ci_dpm_init()
5832 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) in ci_dpm_init()
5835 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) { in ci_dpm_init()
5836 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) in ci_dpm_init()
5838 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) in ci_dpm_init()
5841 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL; in ci_dpm_init()
5844 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) { in ci_dpm_init()
5845 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) in ci_dpm_init()
5847 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) in ci_dpm_init()
5850 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL; in ci_dpm_init()
5857 radeon_acpi_is_pcie_performance_request_supported(rdev); in ci_dpm_init()
5862 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size, in ci_dpm_init()
5873 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) in ci_dpm_init()
5883 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in ci_dpm_init()
5884 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in ci_dpm_init()
5885 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in ci_dpm_init()
5886 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_dpm_init()
5893 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, in ci_dpm_debugfs_print_current_performance_level() argument
5896 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_debugfs_print_current_performance_level()
5898 u32 sclk = ci_get_average_sclk_freq(rdev); in ci_dpm_debugfs_print_current_performance_level()
5899 u32 mclk = ci_get_average_mclk_freq(rdev); in ci_dpm_debugfs_print_current_performance_level()
5907 void ci_dpm_print_power_state(struct radeon_device *rdev, in ci_dpm_print_power_state() argument
5922 r600_dpm_print_ps_status(rdev, rps); in ci_dpm_print_power_state()
5925 u32 ci_dpm_get_current_sclk(struct radeon_device *rdev) in ci_dpm_get_current_sclk() argument
5927 u32 sclk = ci_get_average_sclk_freq(rdev); in ci_dpm_get_current_sclk()
5932 u32 ci_dpm_get_current_mclk(struct radeon_device *rdev) in ci_dpm_get_current_mclk() argument
5934 u32 mclk = ci_get_average_mclk_freq(rdev); in ci_dpm_get_current_mclk()
5939 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low) in ci_dpm_get_sclk() argument
5941 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_get_sclk()
5950 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low) in ci_dpm_get_mclk() argument
5952 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_get_mclk()