Lines Matching refs:fb_location
1146 uint64_t fb_location; in dce4_crtc_do_set_base() local
1179 fb_location = radeon_bo_gpu_offset(rbo); in dce4_crtc_do_set_base()
1181 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); in dce4_crtc_do_set_base()
1376 upper_32_bits(fb_location)); in dce4_crtc_do_set_base()
1378 upper_32_bits(fb_location)); in dce4_crtc_do_set_base()
1380 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); in dce4_crtc_do_set_base()
1382 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); in dce4_crtc_do_set_base()
1463 uint64_t fb_location; in avivo_crtc_do_set_base() local
1495 fb_location = radeon_bo_gpu_offset(rbo); in avivo_crtc_do_set_base()
1497 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); in avivo_crtc_do_set_base()
1583 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); in avivo_crtc_do_set_base()
1584 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); in avivo_crtc_do_set_base()
1586 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); in avivo_crtc_do_set_base()
1587 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); in avivo_crtc_do_set_base()
1591 (u32) fb_location); in avivo_crtc_do_set_base()
1593 radeon_crtc->crtc_offset, (u32) fb_location); in avivo_crtc_do_set_base()