36 nv40_sensor_style(struct nvkm_therm *therm)  in nv40_sensor_style()  argument
38 	struct nvkm_device *device = nv_device(therm);  in nv40_sensor_style()
62 nv40_sensor_setup(struct nvkm_therm *therm)  in nv40_sensor_setup()  argument
64 	enum nv40_sensor_style style = nv40_sensor_style(therm);  in nv40_sensor_setup()
68 		nv_mask(therm, 0x15b8, 0x80000000, 0);  in nv40_sensor_setup()
69 		nv_wr32(therm, 0x15b0, 0x80003fff);  in nv40_sensor_setup()
71 		return nv_rd32(therm, 0x15b4) & 0x3fff;  in nv40_sensor_setup()
73 		nv_wr32(therm, 0x15b0, 0xff);  in nv40_sensor_setup()
75 		return nv_rd32(therm, 0x15b4) & 0xff;  in nv40_sensor_setup()
81 nv40_temp_get(struct nvkm_therm *therm)  in nv40_temp_get()  argument
83 	struct nvkm_therm_priv *priv = (void *)therm;  in nv40_temp_get()
85 	enum nv40_sensor_style style = nv40_sensor_style(therm);  in nv40_temp_get()
89 		nv_wr32(therm, 0x15b0, 0x80003fff);  in nv40_temp_get()
90 		core_temp = nv_rd32(therm, 0x15b4) & 0x3fff;  in nv40_temp_get()
92 		nv_wr32(therm, 0x15b0, 0xff);  in nv40_temp_get()
93 		core_temp = nv_rd32(therm, 0x15b4) & 0xff;  in nv40_temp_get()
114 nv40_fan_pwm_ctrl(struct nvkm_therm *therm, int line, bool enable)  in nv40_fan_pwm_ctrl()  argument
117 	if      (line == 2) nv_mask(therm, 0x0010f0, 0x80000000, mask);  in nv40_fan_pwm_ctrl()
118 	else if (line == 9) nv_mask(therm, 0x0015f4, 0x80000000, mask);  in nv40_fan_pwm_ctrl()
120 		nv_error(therm, "unknown pwm ctrl for gpio %d\n", line);  in nv40_fan_pwm_ctrl()
127 nv40_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty)  in nv40_fan_pwm_get()  argument
130 		u32 reg = nv_rd32(therm, 0x0010f0);  in nv40_fan_pwm_get()
138 		u32 reg = nv_rd32(therm, 0x0015f4);  in nv40_fan_pwm_get()
140 			*divs = nv_rd32(therm, 0x0015f8);  in nv40_fan_pwm_get()
145 		nv_error(therm, "unknown pwm ctrl for gpio %d\n", line);  in nv40_fan_pwm_get()
153 nv40_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty)  in nv40_fan_pwm_set()  argument
156 		nv_mask(therm, 0x0010f0, 0x7fff7fff, (duty << 16) | divs);  in nv40_fan_pwm_set()
159 		nv_wr32(therm, 0x0015f8, divs);  in nv40_fan_pwm_set()
160 		nv_mask(therm, 0x0015f4, 0x7fffffff, duty);  in nv40_fan_pwm_set()
162 		nv_error(therm, "unknown pwm ctrl for gpio %d\n", line);  in nv40_fan_pwm_set()
172 	struct nvkm_therm *therm = nvkm_therm(subdev);  in nv40_therm_intr()  local
173 	uint32_t stat = nv_rd32(therm, 0x1100);  in nv40_therm_intr()
178 	nv_wr32(therm, 0x1100, 0x70000);  in nv40_therm_intr()
180 	nv_error(therm, "THERM received an IRQ: stat = %x\n", stat);  in nv40_therm_intr()
209 	struct nvkm_therm *therm = (void *)object;  in nv40_therm_init()  local
211 	nv40_sensor_setup(therm);  in nv40_therm_init()