33 pwm_info(struct nvkm_therm *therm, int line)  in pwm_info()  argument
35 	u32 gpio = nv_rd32(therm, 0x00d610 + (line * 0x04));  in pwm_info()
52 	nv_error(therm, "GPIO %d unknown PWM: 0x%08x\n", line, gpio);  in pwm_info()
57 gf110_fan_pwm_ctrl(struct nvkm_therm *therm, int line, bool enable)  in gf110_fan_pwm_ctrl()  argument
60 	int indx = pwm_info(therm, line);  in gf110_fan_pwm_ctrl()
64 		nv_mask(therm, 0x00d610 + (line * 0x04), 0x000000c0, data);  in gf110_fan_pwm_ctrl()
70 gf110_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty)  in gf110_fan_pwm_get()  argument
72 	int indx = pwm_info(therm, line);  in gf110_fan_pwm_get()
76 		if (nv_rd32(therm, 0x00d610 + (line * 0x04)) & 0x00000040) {  in gf110_fan_pwm_get()
77 			*divs = nv_rd32(therm, 0x00e114 + (indx * 8));  in gf110_fan_pwm_get()
78 			*duty = nv_rd32(therm, 0x00e118 + (indx * 8));  in gf110_fan_pwm_get()
82 		*divs = nv_rd32(therm, 0x0200d8) & 0x1fff;  in gf110_fan_pwm_get()
83 		*duty = nv_rd32(therm, 0x0200dc) & 0x1fff;  in gf110_fan_pwm_get()
91 gf110_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty)  in gf110_fan_pwm_set()  argument
93 	int indx = pwm_info(therm, line);  in gf110_fan_pwm_set()
97 		nv_wr32(therm, 0x00e114 + (indx * 8), divs);  in gf110_fan_pwm_set()
98 		nv_wr32(therm, 0x00e118 + (indx * 8), duty | 0x80000000);  in gf110_fan_pwm_set()
100 		nv_mask(therm, 0x0200d8, 0x1fff, divs); /* keep the high bits */  in gf110_fan_pwm_set()
101 		nv_wr32(therm, 0x0200dc, duty | 0x40000000);  in gf110_fan_pwm_set()
107 gf110_fan_pwm_clock(struct nvkm_therm *therm, int line)  in gf110_fan_pwm_clock()  argument
109 	int indx = pwm_info(therm, line);  in gf110_fan_pwm_clock()
113 		return (nv_device(therm)->crystal * 1000) / 20;  in gf110_fan_pwm_clock()
115 		return nv_device(therm)->crystal * 1000 / 10;  in gf110_fan_pwm_clock()