39 nv44_vm_fill(struct nvkm_gpuobj *pgt, dma_addr_t null,  in nv44_vm_fill()  argument
45 	tmp[0] = nv_ro32(pgt, base + 0x0);  in nv44_vm_fill()
46 	tmp[1] = nv_ro32(pgt, base + 0x4);  in nv44_vm_fill()
47 	tmp[2] = nv_ro32(pgt, base + 0x8);  in nv44_vm_fill()
48 	tmp[3] = nv_ro32(pgt, base + 0xc);  in nv44_vm_fill()
78 	nv_wo32(pgt, base + 0x0, tmp[0]);  in nv44_vm_fill()
79 	nv_wo32(pgt, base + 0x4, tmp[1]);  in nv44_vm_fill()
80 	nv_wo32(pgt, base + 0x8, tmp[2]);  in nv44_vm_fill()
81 	nv_wo32(pgt, base + 0xc, tmp[3] | 0x40000000);  in nv44_vm_fill()
85 nv44_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,  in nv44_vm_map_sg()  argument
95 		nv44_vm_fill(pgt, priv->null, list, pte, part);  in nv44_vm_map_sg()
104 		nv_wo32(pgt, pte++ * 4, tmp[0] >>  0 | tmp[1] << 27);  in nv44_vm_map_sg()
105 		nv_wo32(pgt, pte++ * 4, tmp[1] >>  5 | tmp[2] << 22);  in nv44_vm_map_sg()
106 		nv_wo32(pgt, pte++ * 4, tmp[2] >> 10 | tmp[3] << 17);  in nv44_vm_map_sg()
107 		nv_wo32(pgt, pte++ * 4, tmp[3] >> 15 | 0x40000000);  in nv44_vm_map_sg()
112 		nv44_vm_fill(pgt, priv->null, list, pte, cnt);  in nv44_vm_map_sg()
116 nv44_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)  in nv44_vm_unmap()  argument
118 	struct nv04_mmu_priv *priv = (void *)nvkm_mmu(pgt);  in nv44_vm_unmap()
123 		nv44_vm_fill(pgt, priv->null, NULL, pte, part);  in nv44_vm_unmap()
129 		nv_wo32(pgt, pte++ * 4, 0x00000000);  in nv44_vm_unmap()
130 		nv_wo32(pgt, pte++ * 4, 0x00000000);  in nv44_vm_unmap()
131 		nv_wo32(pgt, pte++ * 4, 0x00000000);  in nv44_vm_unmap()
132 		nv_wo32(pgt, pte++ * 4, 0x00000000);  in nv44_vm_unmap()
137 		nv44_vm_fill(pgt, priv->null, NULL, pte, cnt);  in nv44_vm_unmap()
200 			      &priv->vm->pgt[0].obj[0]);  in nv44_mmu_ctor()
201 	priv->vm->pgt[0].refcount[0] = 1;  in nv44_mmu_ctor()
212 	struct nvkm_gpuobj *gart = priv->vm->pgt[0].obj[0];  in nv44_mmu_init()