27 nv50_gpio_reset(struct nvkm_gpio *gpio, u8 match)  in nv50_gpio_reset()  argument
29 	struct nvkm_bios *bios = nvkm_bios(gpio);  in nv50_gpio_reset()
50 		gpio->set(gpio, 0, func, line, defs);  in nv50_gpio_reset()
52 		nv_mask(gpio, reg, 0x00010001 << lsh, val << lsh);  in nv50_gpio_reset()
70 nv50_gpio_drive(struct nvkm_gpio *gpio, int line, int dir, int out)  in nv50_gpio_drive()  argument
77 	nv_mask(gpio, reg, 3 << shift, (((dir ^ 1) << 1) | out) << shift);  in nv50_gpio_drive()
82 nv50_gpio_sense(struct nvkm_gpio *gpio, int line)  in nv50_gpio_sense()  argument
89 	return !!(nv_rd32(gpio, reg) & (4 << shift));  in nv50_gpio_sense()
93 nv50_gpio_intr_stat(struct nvkm_gpio *gpio, u32 *hi, u32 *lo)  in nv50_gpio_intr_stat()  argument
95 	u32 intr = nv_rd32(gpio, 0x00e054);  in nv50_gpio_intr_stat()
96 	u32 stat = nv_rd32(gpio, 0x00e050) & intr;  in nv50_gpio_intr_stat()
99 	nv_wr32(gpio, 0x00e054, intr);  in nv50_gpio_intr_stat()
103 nv50_gpio_intr_mask(struct nvkm_gpio *gpio, u32 type, u32 mask, u32 data)  in nv50_gpio_intr_mask()  argument
105 	u32 inte = nv_rd32(gpio, 0x00e050);  in nv50_gpio_intr_mask()
110 	nv_wr32(gpio, 0x00e050, inte);  in nv50_gpio_intr_mask()