Lines Matching refs:hwsq
36 struct hwsq base;
55 struct nv50_ramseq hwsq; member
65 struct nv50_ramseq *hwsq = &ram->hwsq; in nv50_ram_calc() local
112 ret = ram_init(hwsq, nv_subdev(pfb)); in nv50_ram_calc()
116 ram_wait(hwsq, 0x01, 0x00); /* wait for !vblank */ in nv50_ram_calc()
117 ram_wait(hwsq, 0x01, 0x01); /* wait for vblank */ in nv50_ram_calc()
118 ram_wr32(hwsq, 0x611200, 0x00003300); in nv50_ram_calc()
119 ram_wr32(hwsq, 0x002504, 0x00000001); /* block fifo */ in nv50_ram_calc()
120 ram_nsec(hwsq, 8000); in nv50_ram_calc()
121 ram_setf(hwsq, 0x10, 0x00); /* disable fb */ in nv50_ram_calc()
122 ram_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */ in nv50_ram_calc()
124 ram_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge */ in nv50_ram_calc()
125 ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */ in nv50_ram_calc()
126 ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */ in nv50_ram_calc()
127 ram_wr32(hwsq, 0x100210, 0x00000000); /* disable auto-refresh */ in nv50_ram_calc()
128 ram_wr32(hwsq, 0x1002dc, 0x00000001); /* enable self-refresh */ in nv50_ram_calc()
142 ram_mask(hwsq, 0x00c040, 0xc000c000, 0x0000c000); in nv50_ram_calc()
143 ram_mask(hwsq, 0x004008, 0x00000200, 0x00000200); in nv50_ram_calc()
144 ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1); in nv50_ram_calc()
145 ram_mask(hwsq, 0x004008, 0x81ff0000, 0x80000000 | (mpll.bias_p << 19) | in nv50_ram_calc()
149 ram_mask(hwsq, 0x100da0[i], 0x00000000, 0x00000000); /*XXX*/ in nv50_ram_calc()
151 ram_nsec(hwsq, 96000); /*XXX*/ in nv50_ram_calc()
152 ram_mask(hwsq, 0x004008, 0x00002200, 0x00002000); in nv50_ram_calc()
154 ram_wr32(hwsq, 0x1002dc, 0x00000000); /* disable self-refresh */ in nv50_ram_calc()
155 ram_wr32(hwsq, 0x100210, 0x80000000); /* enable auto-refresh */ in nv50_ram_calc()
157 ram_nsec(hwsq, 12000); in nv50_ram_calc()
161 ram_nuke(hwsq, mr[0]); /* force update */ in nv50_ram_calc()
162 ram_mask(hwsq, mr[0], 0x000, 0x000); in nv50_ram_calc()
165 ram_mask(hwsq, mr[2], 0x000, 0x000); in nv50_ram_calc()
166 ram_nuke(hwsq, mr[0]); /* force update */ in nv50_ram_calc()
167 ram_mask(hwsq, mr[0], 0x000, 0x000); in nv50_ram_calc()
173 ram_mask(hwsq, timing[3], 0x00000000, 0x00000000); /*XXX*/ in nv50_ram_calc()
174 ram_mask(hwsq, timing[1], 0x00000000, 0x00000000); /*XXX*/ in nv50_ram_calc()
175 ram_mask(hwsq, timing[6], 0x00000000, 0x00000000); /*XXX*/ in nv50_ram_calc()
176 ram_mask(hwsq, timing[7], 0x00000000, 0x00000000); /*XXX*/ in nv50_ram_calc()
177 ram_mask(hwsq, timing[8], 0x00000000, 0x00000000); /*XXX*/ in nv50_ram_calc()
178 ram_mask(hwsq, timing[0], 0x00000000, 0x00000000); /*XXX*/ in nv50_ram_calc()
179 ram_mask(hwsq, timing[2], 0x00000000, 0x00000000); /*XXX*/ in nv50_ram_calc()
180 ram_mask(hwsq, timing[4], 0x00000000, 0x00000000); /*XXX*/ in nv50_ram_calc()
181 ram_mask(hwsq, timing[5], 0x00000000, 0x00000000); /*XXX*/ in nv50_ram_calc()
183 ram_mask(hwsq, timing[0], 0x00000000, 0x00000000); /*XXX*/ in nv50_ram_calc()
186 ram_nuke(hwsq, 0x100e24); in nv50_ram_calc()
187 ram_mask(hwsq, 0x100e24, 0x00000000, 0x00000000); in nv50_ram_calc()
188 ram_nuke(hwsq, 0x100e20); in nv50_ram_calc()
189 ram_mask(hwsq, 0x100e20, 0x00000000, 0x00000000); in nv50_ram_calc()
192 ram_mask(hwsq, mr[0], 0x100, 0x100); in nv50_ram_calc()
193 ram_mask(hwsq, mr[0], 0x100, 0x000); in nv50_ram_calc()
195 ram_setf(hwsq, 0x10, 0x01); /* enable fb */ in nv50_ram_calc()
196 ram_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */ in nv50_ram_calc()
197 ram_wr32(hwsq, 0x611200, 0x00003330); in nv50_ram_calc()
198 ram_wr32(hwsq, 0x002504, 0x00000000); /* un-block fifo */ in nv50_ram_calc()
207 struct nv50_ramseq *hwsq = &ram->hwsq; in nv50_ram_prog() local
209 ram_exec(hwsq, nvkm_boolopt(device->cfgopt, "NvMemExec", true)); in nv50_ram_prog()
217 struct nv50_ramseq *hwsq = &ram->hwsq; in nv50_ram_tidy() local
218 ram_exec(hwsq, false); in nv50_ram_tidy()
425 ram->hwsq.r_0x002504 = hwsq_reg(0x002504); in nv50_ram_ctor()
426 ram->hwsq.r_0x00c040 = hwsq_reg(0x00c040); in nv50_ram_ctor()
427 ram->hwsq.r_0x004008 = hwsq_reg(0x004008); in nv50_ram_ctor()
428 ram->hwsq.r_0x00400c = hwsq_reg(0x00400c); in nv50_ram_ctor()
429 ram->hwsq.r_0x100210 = hwsq_reg(0x100210); in nv50_ram_ctor()
430 ram->hwsq.r_0x1002d0 = hwsq_reg(0x1002d0); in nv50_ram_ctor()
431 ram->hwsq.r_0x1002d4 = hwsq_reg(0x1002d4); in nv50_ram_ctor()
432 ram->hwsq.r_0x1002dc = hwsq_reg(0x1002dc); in nv50_ram_ctor()
434 ram->hwsq.r_0x100da0[i] = hwsq_reg(0x100da0 + (i * 0x04)); in nv50_ram_ctor()
435 ram->hwsq.r_0x100e20 = hwsq_reg(0x100e20); in nv50_ram_ctor()
436 ram->hwsq.r_0x100e24 = hwsq_reg(0x100e24); in nv50_ram_ctor()
437 ram->hwsq.r_0x611200 = hwsq_reg(0x611200); in nv50_ram_ctor()
440 ram->hwsq.r_timing[i] = hwsq_reg(0x100220 + (i * 0x04)); in nv50_ram_ctor()
443 ram->hwsq.r_mr[0] = hwsq_reg2(0x1002c0, 0x1002c8); in nv50_ram_ctor()
444 ram->hwsq.r_mr[1] = hwsq_reg2(0x1002c4, 0x1002cc); in nv50_ram_ctor()
445 ram->hwsq.r_mr[2] = hwsq_reg2(0x1002e0, 0x1002e8); in nv50_ram_ctor()
446 ram->hwsq.r_mr[3] = hwsq_reg2(0x1002e4, 0x1002ec); in nv50_ram_ctor()
448 ram->hwsq.r_mr[0] = hwsq_reg(0x1002c0); in nv50_ram_ctor()
449 ram->hwsq.r_mr[1] = hwsq_reg(0x1002c4); in nv50_ram_ctor()
450 ram->hwsq.r_mr[2] = hwsq_reg(0x1002e0); in nv50_ram_ctor()
451 ram->hwsq.r_mr[3] = hwsq_reg(0x1002e4); in nv50_ram_ctor()