38 	struct nv40_ram *ram = (void *)pfb->ram;  in nv40_ram_calc()  local
54 	ram->ctrl  = 0x80000000 | (log2P << 16);  in nv40_ram_calc()
55 	ram->ctrl |= min(pll.bias_p + log2P, (int)pll.max_p) << 20;  in nv40_ram_calc()
57 		ram->ctrl |= 0x00000100;  in nv40_ram_calc()
58 		ram->coef  = (N1 << 8) | M1;  in nv40_ram_calc()
60 		ram->ctrl |= 0x40000000;  in nv40_ram_calc()
61 		ram->coef  = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1;  in nv40_ram_calc()
71 	struct nv40_ram *ram = (void *)pfb->ram;  in nv40_ram_prog()  local
118 		nv_mask(pfb, 0x004044, 0xc0771100, ram->ctrl);  in nv40_ram_prog()
119 		nv_mask(pfb, 0x00402c, 0xc0771100, ram->ctrl);  in nv40_ram_prog()
120 		nv_wr32(pfb, 0x004048, ram->coef);  in nv40_ram_prog()
121 		nv_wr32(pfb, 0x004030, ram->coef);  in nv40_ram_prog()
125 		nv_mask(pfb, 0x004038, 0xc0771100, ram->ctrl);  in nv40_ram_prog()
126 		nv_wr32(pfb, 0x00403c, ram->coef);  in nv40_ram_prog()
128 		nv_mask(pfb, 0x004020, 0xc0771100, ram->ctrl);  in nv40_ram_prog()
129 		nv_wr32(pfb, 0x004024, ram->coef);  in nv40_ram_prog()
177 	struct nv40_ram *ram;  in nv40_ram_create()  local
181 	ret = nvkm_ram_create(parent, engine, oclass, &ram);  in nv40_ram_create()
182 	*pobject = nv_object(ram);  in nv40_ram_create()
187 	case 0x00000000: ram->base.type = NV_MEM_TYPE_SDRAM; break;  in nv40_ram_create()
188 	case 0x00000100: ram->base.type = NV_MEM_TYPE_DDR1; break;  in nv40_ram_create()
189 	case 0x00000200: ram->base.type = NV_MEM_TYPE_GDDR3; break;  in nv40_ram_create()
190 	case 0x00000300: ram->base.type = NV_MEM_TYPE_DDR2; break;  in nv40_ram_create()
193 	ram->base.size  =  nv_rd32(pfb, 0x10020c) & 0xff000000;  in nv40_ram_create()
194 	ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;  in nv40_ram_create()
195 	ram->base.tags  =  nv_rd32(pfb, 0x100320);  in nv40_ram_create()
196 	ram->base.calc = nv40_ram_calc;  in nv40_ram_create()
197 	ram->base.prog = nv40_ram_prog;  in nv40_ram_create()
198 	ram->base.tidy = nv40_ram_tidy;  in nv40_ram_create()