35 nv40_ram_calc(struct nvkm_fb *pfb, u32 freq)  in nv40_ram_calc()  argument
37 	struct nvkm_bios *bios = nvkm_bios(pfb);  in nv40_ram_calc()
38 	struct nv40_ram *ram = (void *)pfb->ram;  in nv40_ram_calc()
45 		nv_error(pfb, "mclk pll data not found\n");  in nv40_ram_calc()
49 	ret = nv04_pll_calc(nv_subdev(pfb), &pll, freq,  in nv40_ram_calc()
68 nv40_ram_prog(struct nvkm_fb *pfb)  in nv40_ram_prog()  argument
70 	struct nvkm_bios *bios = nvkm_bios(pfb);  in nv40_ram_prog()
71 	struct nv40_ram *ram = (void *)pfb->ram;  in nv40_ram_prog()
79 		u32 vbl = nv_rd32(pfb, 0x600808 + (i * 0x2000));  in nv40_ram_prog()
82 			if (vbl != nv_rd32(pfb, 0x600808 + (i * 0x2000))) {  in nv40_ram_prog()
83 				nv_wr08(pfb, 0x0c03c4 + (i * 0x2000), 0x01);  in nv40_ram_prog()
84 				sr1[i] = nv_rd08(pfb, 0x0c03c5 + (i * 0x2000));  in nv40_ram_prog()
97 		nv_wait(pfb, 0x600808 + (i * 0x2000), 0x00010000, 0x00000000);  in nv40_ram_prog()
98 		nv_wait(pfb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);  in nv40_ram_prog()
99 		nv_wr08(pfb, 0x0c03c4 + (i * 0x2000), 0x01);  in nv40_ram_prog()
100 		nv_wr08(pfb, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20);  in nv40_ram_prog()
104 	nv_wr32(pfb, 0x1002d4, 0x00000001); /* precharge */  in nv40_ram_prog()
105 	nv_wr32(pfb, 0x1002d0, 0x00000001); /* refresh */  in nv40_ram_prog()
106 	nv_wr32(pfb, 0x1002d0, 0x00000001); /* refresh */  in nv40_ram_prog()
107 	nv_mask(pfb, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */  in nv40_ram_prog()
108 	nv_wr32(pfb, 0x1002dc, 0x00000001); /* enable self-refresh */  in nv40_ram_prog()
111 	nv_mask(pfb, 0x00c040, 0x0000c000, 0x00000000);  in nv40_ram_prog()
112 	switch (nv_device(pfb)->chipset) {  in nv40_ram_prog()
118 		nv_mask(pfb, 0x004044, 0xc0771100, ram->ctrl);  in nv40_ram_prog()
119 		nv_mask(pfb, 0x00402c, 0xc0771100, ram->ctrl);  in nv40_ram_prog()
120 		nv_wr32(pfb, 0x004048, ram->coef);  in nv40_ram_prog()
121 		nv_wr32(pfb, 0x004030, ram->coef);  in nv40_ram_prog()
125 		nv_mask(pfb, 0x004038, 0xc0771100, ram->ctrl);  in nv40_ram_prog()
126 		nv_wr32(pfb, 0x00403c, ram->coef);  in nv40_ram_prog()
128 		nv_mask(pfb, 0x004020, 0xc0771100, ram->ctrl);  in nv40_ram_prog()
129 		nv_wr32(pfb, 0x004024, ram->coef);  in nv40_ram_prog()
133 	nv_mask(pfb, 0x00c040, 0x0000c000, 0x0000c000);  in nv40_ram_prog()
136 	nv_wr32(pfb, 0x1002dc, 0x00000000);  in nv40_ram_prog()
137 	nv_mask(pfb, 0x100210, 0x80000000, 0x80000000);  in nv40_ram_prog()
143 			.subdev = nv_subdev(pfb),  in nv40_ram_prog()
158 		nv_wait(pfb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);  in nv40_ram_prog()
159 		nv_wr08(pfb, 0x0c03c4 + (i * 0x2000), 0x01);  in nv40_ram_prog()
160 		nv_wr08(pfb, 0x0c03c5 + (i * 0x2000), sr1[i]);  in nv40_ram_prog()
167 nv40_ram_tidy(struct nvkm_fb *pfb)  in nv40_ram_tidy()  argument
176 	struct nvkm_fb *pfb = nvkm_fb(parent);  in nv40_ram_create()  local
178 	u32 pbus1218 = nv_rd32(pfb, 0x001218);  in nv40_ram_create()
193 	ram->base.size  =  nv_rd32(pfb, 0x10020c) & 0xff000000;  in nv40_ram_create()
194 	ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1;  in nv40_ram_create()
195 	ram->base.tags  =  nv_rd32(pfb, 0x100320);  in nv40_ram_create()