Lines Matching refs:bios
82 pll_limits_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) in pll_limits_table() argument
86 if (!bit_entry(bios, 'C', &bit_C) && bit_C.length >= 10) { in pll_limits_table()
87 u16 data = nv_ro16(bios, bit_C.offset + 8); in pll_limits_table()
89 *ver = nv_ro08(bios, data + 0); in pll_limits_table()
90 *hdr = nv_ro08(bios, data + 1); in pll_limits_table()
91 *len = nv_ro08(bios, data + 2); in pll_limits_table()
92 *cnt = nv_ro08(bios, data + 3); in pll_limits_table()
97 if (bmp_version(bios) >= 0x0524) { in pll_limits_table()
98 u16 data = nv_ro16(bios, bios->bmp_offset + 142); in pll_limits_table()
100 *ver = nv_ro08(bios, data + 0); in pll_limits_table()
113 pll_map(struct nvkm_bios *bios) in pll_map() argument
115 switch (nv_device(bios)->card_type) { in pll_map()
126 if (nv_device(bios)->chipset == 0x50) in pll_map()
129 if (nv_device(bios)->chipset < 0xa3 || in pll_map()
130 nv_device(bios)->chipset == 0xaa || in pll_map()
131 nv_device(bios)->chipset == 0xac) in pll_map()
139 pll_map_reg(struct nvkm_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len) in pll_map_reg() argument
145 data = pll_limits_table(bios, ver, &hdr, &cnt, len); in pll_map_reg()
149 if (nv_ro32(bios, data + 3) == reg) { in pll_map_reg()
150 *type = nv_ro08(bios, data + 0); in pll_map_reg()
158 map = pll_map(bios); in pll_map_reg()
164 if (nv_ro32(bios, data) == map->reg) in pll_map_reg()
181 pll_map_type(struct nvkm_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len) in pll_map_type() argument
187 data = pll_limits_table(bios, ver, &hdr, &cnt, len); in pll_map_type()
191 if (nv_ro08(bios, data + 0) == type) { in pll_map_type()
192 *reg = nv_ro32(bios, data + 3); in pll_map_type()
200 map = pll_map(bios); in pll_map_type()
206 if (nv_ro32(bios, data) == map->reg) in pll_map_type()
223 nvbios_pll_parse(struct nvkm_bios *bios, u32 type, struct nvbios_pll *info) in nvbios_pll_parse() argument
231 data = pll_map_reg(bios, reg, &type, &ver, &len); in nvbios_pll_parse()
233 data = pll_map_type(bios, type, ®, &ver, &len); in nvbios_pll_parse()
248 info->vco1.min_freq = nv_ro32(bios, data + 0); in nvbios_pll_parse()
249 info->vco1.max_freq = nv_ro32(bios, data + 4); in nvbios_pll_parse()
250 info->vco2.min_freq = nv_ro32(bios, data + 8); in nvbios_pll_parse()
251 info->vco2.max_freq = nv_ro32(bios, data + 12); in nvbios_pll_parse()
252 info->vco1.min_inputfreq = nv_ro32(bios, data + 16); in nvbios_pll_parse()
253 info->vco2.min_inputfreq = nv_ro32(bios, data + 20); in nvbios_pll_parse()
261 switch (bios->version.chip) { in nvbios_pll_parse()
280 switch (bios->version.chip) { in nvbios_pll_parse()
294 info->vco1.min_freq = nv_ro16(bios, data + 4) * 1000; in nvbios_pll_parse()
295 info->vco1.max_freq = nv_ro16(bios, data + 6) * 1000; in nvbios_pll_parse()
296 info->vco2.min_freq = nv_ro16(bios, data + 8) * 1000; in nvbios_pll_parse()
297 info->vco2.max_freq = nv_ro16(bios, data + 10) * 1000; in nvbios_pll_parse()
298 info->vco1.min_inputfreq = nv_ro16(bios, data + 12) * 1000; in nvbios_pll_parse()
299 info->vco2.min_inputfreq = nv_ro16(bios, data + 14) * 1000; in nvbios_pll_parse()
300 info->vco1.max_inputfreq = nv_ro16(bios, data + 16) * 1000; in nvbios_pll_parse()
301 info->vco2.max_inputfreq = nv_ro16(bios, data + 18) * 1000; in nvbios_pll_parse()
302 info->vco1.min_n = nv_ro08(bios, data + 20); in nvbios_pll_parse()
303 info->vco1.max_n = nv_ro08(bios, data + 21); in nvbios_pll_parse()
304 info->vco1.min_m = nv_ro08(bios, data + 22); in nvbios_pll_parse()
305 info->vco1.max_m = nv_ro08(bios, data + 23); in nvbios_pll_parse()
306 info->vco2.min_n = nv_ro08(bios, data + 24); in nvbios_pll_parse()
307 info->vco2.max_n = nv_ro08(bios, data + 25); in nvbios_pll_parse()
308 info->vco2.min_m = nv_ro08(bios, data + 26); in nvbios_pll_parse()
309 info->vco2.max_m = nv_ro08(bios, data + 27); in nvbios_pll_parse()
311 info->max_p = nv_ro08(bios, data + 29); in nvbios_pll_parse()
313 if (bios->version.chip < 0x60) in nvbios_pll_parse()
315 info->bias_p = nv_ro08(bios, data + 30); in nvbios_pll_parse()
318 info->refclk = nv_ro32(bios, data + 31); in nvbios_pll_parse()
321 data = nv_ro16(bios, data + 1); in nvbios_pll_parse()
323 info->vco1.min_freq = nv_ro16(bios, data + 0) * 1000; in nvbios_pll_parse()
324 info->vco1.max_freq = nv_ro16(bios, data + 2) * 1000; in nvbios_pll_parse()
325 info->vco2.min_freq = nv_ro16(bios, data + 4) * 1000; in nvbios_pll_parse()
326 info->vco2.max_freq = nv_ro16(bios, data + 6) * 1000; in nvbios_pll_parse()
327 info->vco1.min_inputfreq = nv_ro16(bios, data + 8) * 1000; in nvbios_pll_parse()
328 info->vco2.min_inputfreq = nv_ro16(bios, data + 10) * 1000; in nvbios_pll_parse()
329 info->vco1.max_inputfreq = nv_ro16(bios, data + 12) * 1000; in nvbios_pll_parse()
330 info->vco2.max_inputfreq = nv_ro16(bios, data + 14) * 1000; in nvbios_pll_parse()
331 info->vco1.min_n = nv_ro08(bios, data + 16); in nvbios_pll_parse()
332 info->vco1.max_n = nv_ro08(bios, data + 17); in nvbios_pll_parse()
333 info->vco1.min_m = nv_ro08(bios, data + 18); in nvbios_pll_parse()
334 info->vco1.max_m = nv_ro08(bios, data + 19); in nvbios_pll_parse()
335 info->vco2.min_n = nv_ro08(bios, data + 20); in nvbios_pll_parse()
336 info->vco2.max_n = nv_ro08(bios, data + 21); in nvbios_pll_parse()
337 info->vco2.min_m = nv_ro08(bios, data + 22); in nvbios_pll_parse()
338 info->vco2.max_m = nv_ro08(bios, data + 23); in nvbios_pll_parse()
339 info->max_p_usable = info->max_p = nv_ro08(bios, data + 25); in nvbios_pll_parse()
340 info->bias_p = nv_ro08(bios, data + 27); in nvbios_pll_parse()
341 info->refclk = nv_ro32(bios, data + 28); in nvbios_pll_parse()
344 info->refclk = nv_ro16(bios, data + 9) * 1000; in nvbios_pll_parse()
345 data = nv_ro16(bios, data + 1); in nvbios_pll_parse()
347 info->vco1.min_freq = nv_ro16(bios, data + 0) * 1000; in nvbios_pll_parse()
348 info->vco1.max_freq = nv_ro16(bios, data + 2) * 1000; in nvbios_pll_parse()
349 info->vco1.min_inputfreq = nv_ro16(bios, data + 4) * 1000; in nvbios_pll_parse()
350 info->vco1.max_inputfreq = nv_ro16(bios, data + 6) * 1000; in nvbios_pll_parse()
351 info->vco1.min_m = nv_ro08(bios, data + 8); in nvbios_pll_parse()
352 info->vco1.max_m = nv_ro08(bios, data + 9); in nvbios_pll_parse()
353 info->vco1.min_n = nv_ro08(bios, data + 10); in nvbios_pll_parse()
354 info->vco1.max_n = nv_ro08(bios, data + 11); in nvbios_pll_parse()
355 info->min_p = nv_ro08(bios, data + 12); in nvbios_pll_parse()
356 info->max_p = nv_ro08(bios, data + 13); in nvbios_pll_parse()
359 nv_error(bios, "unknown pll limits version 0x%02x\n", ver); in nvbios_pll_parse()
364 info->refclk = nv_device(bios)->crystal; in nvbios_pll_parse()
365 if (bios->version.chip == 0x51) { in nvbios_pll_parse()
366 u32 sel_clk = nv_rd32(bios, 0x680524); in nvbios_pll_parse()
369 if (nv_rdvgac(bios, 0, 0x27) < 0xa3) in nvbios_pll_parse()
383 info->vco1.max_freq = nv_ro32(bios, bios->bmp_offset + 67); in nvbios_pll_parse()
384 info->vco1.min_freq = nv_ro32(bios, bios->bmp_offset + 71); in nvbios_pll_parse()
385 if (bmp_version(bios) < 0x0506) { in nvbios_pll_parse()
396 if (nv_device(bios)->crystal == 13500) { in nvbios_pll_parse()
398 if (bios->version.chip < 0x11) in nvbios_pll_parse()
402 if (bios->version.chip < 0x11) in nvbios_pll_parse()
407 if (bios->version.chip < 0x17 || in nvbios_pll_parse()
408 bios->version.chip == 0x1a || in nvbios_pll_parse()
409 bios->version.chip == 0x20) in nvbios_pll_parse()