1268 	struct nvkm_gpuobj *chan;  in gf100_grctx_generate()  local
1276 			      0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan);  in gf100_grctx_generate()
1283 	nv_wo32(chan, 0x0200, lower_32_bits(chan->addr + 0x1000));  in gf100_grctx_generate()
1284 	nv_wo32(chan, 0x0204, upper_32_bits(chan->addr + 0x1000));  in gf100_grctx_generate()
1285 	nv_wo32(chan, 0x0208, 0xffffffff);  in gf100_grctx_generate()
1286 	nv_wo32(chan, 0x020c, 0x000000ff);  in gf100_grctx_generate()
1289 	nv_wo32(chan, 0x1000, 0x00000000);  in gf100_grctx_generate()
1290 	nv_wo32(chan, 0x1004, 0x00000001 | (chan->addr + 0x2000) >> 8);  in gf100_grctx_generate()
1293 	for (i = 0; i < chan->size / 4096; i++) {  in gf100_grctx_generate()
1294 		u64 addr = ((chan->addr + (i * 4096)) >> 8) | 1;  in gf100_grctx_generate()
1295 		nv_wo32(chan, 0x2000 + (i * 8), lower_32_bits(addr));  in gf100_grctx_generate()
1296 		nv_wo32(chan, 0x2004 + (i * 8), upper_32_bits(addr));  in gf100_grctx_generate()
1300 	nv_wo32(chan, 0x0210, 0x00080004);  in gf100_grctx_generate()
1301 	nv_wo32(chan, 0x0214, 0x00000000);  in gf100_grctx_generate()
1305 	nv_wr32(priv, 0x100cb8, (chan->addr + 0x1000) >> 8);  in gf100_grctx_generate()
1319 		nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12);  in gf100_grctx_generate()
1324 		nv_wo32(chan, 0x8001c, 1);  in gf100_grctx_generate()
1325 		nv_wo32(chan, 0x80020, 0);  in gf100_grctx_generate()
1326 		nv_wo32(chan, 0x80028, 0);  in gf100_grctx_generate()
1327 		nv_wo32(chan, 0x8002c, 0);  in gf100_grctx_generate()
1331 		nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12);  in gf100_grctx_generate()
1353 			priv->data[i / 4] = nv_ro32(chan, 0x80000 + i);  in gf100_grctx_generate()
1360 	nvkm_gpuobj_ref(NULL, &chan);  in gf100_grctx_generate()