61 	int chid = impl->chid + head;  in nv50_disp_chan_create_()  local
64 	if (base->chan & (1 << chid))  in nv50_disp_chan_create_()
66 	base->chan |= (1 << chid);  in nv50_disp_chan_create_()
74 	chan->chid = chid;  in nv50_disp_chan_create_()
85 	base->chan &= ~(1 << chan->chid);  in nv50_disp_chan_destroy()
106 nv50_disp_chan_uevent_send(struct nv50_disp_priv *priv, int chid)  in nv50_disp_chan_uevent_send()  argument
111 	nvkm_event_send(&priv->uevent, 1, chid, &rep, sizeof(rep));  in nv50_disp_chan_uevent_send()
127 		notify->index = dmac->base.chid;  in nv50_disp_chan_uevent_ctor()
161 		0x640000 + (chan->chid * 0x1000);  in nv50_disp_chan_map()
171 	return nv_rd32(priv, 0x640000 + (chan->chid * 0x1000) + addr);  in nv50_disp_chan_rd32()
179 	nv_wr32(priv, 0x640000 + (chan->chid * 0x1000) + addr, data);  in nv50_disp_chan_wr32()
193 	u32 chid = chan->chid;  in nv50_disp_dmac_object_attach()  local
194 	u32 data = (chid << 28) | (addr << 10) | chid;  in nv50_disp_dmac_object_attach()
195 	return nvkm_ramht_insert(base->ramht, chid, name, data);  in nv50_disp_dmac_object_attach()
261 	int chid = dmac->base.chid;  in nv50_disp_dmac_init()  local
269 	nv_mask(priv, 0x610028, 0x00010000 << chid, 0x00010000 << chid);  in nv50_disp_dmac_init()
272 	nv_wr32(priv, 0x610204 + (chid * 0x0010), dmac->push);  in nv50_disp_dmac_init()
273 	nv_wr32(priv, 0x610208 + (chid * 0x0010), 0x00010000);  in nv50_disp_dmac_init()
274 	nv_wr32(priv, 0x61020c + (chid * 0x0010), chid);  in nv50_disp_dmac_init()
275 	nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000010, 0x00000010);  in nv50_disp_dmac_init()
276 	nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000);  in nv50_disp_dmac_init()
277 	nv_wr32(priv, 0x610200 + (chid * 0x0010), 0x00000013);  in nv50_disp_dmac_init()
280 	if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x80000000, 0x00000000)) {  in nv50_disp_dmac_init()
282 			 nv_rd32(priv, 0x610200 + (chid * 0x10)));  in nv50_disp_dmac_init()
294 	int chid = dmac->base.chid;  in nv50_disp_dmac_fini()  local
297 	nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00001010, 0x00001000);  in nv50_disp_dmac_fini()
298 	nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000003, 0x00000000);  in nv50_disp_dmac_fini()
299 	if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x001e0000, 0x00000000)) {  in nv50_disp_dmac_fini()
301 			 nv_rd32(priv, 0x610200 + (chid * 0x10)));  in nv50_disp_dmac_fini()
307 	nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00000000 << chid);  in nv50_disp_dmac_fini()
584 	.chid = 0,
686 	.chid = 1,
776 	.chid = 3,
807 	int chid = pioc->base.chid;  in nv50_disp_pioc_init()  local
814 	nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00002000);  in nv50_disp_pioc_init()
815 	if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00000000, 0x00000000)) {  in nv50_disp_pioc_init()
817 			 nv_rd32(priv, 0x610200 + (chid * 0x10)));  in nv50_disp_pioc_init()
821 	nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00000001);  in nv50_disp_pioc_init()
822 	if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00010000)) {  in nv50_disp_pioc_init()
824 			 nv_rd32(priv, 0x610200 + (chid * 0x10)));  in nv50_disp_pioc_init()
836 	int chid = pioc->base.chid;  in nv50_disp_pioc_fini()  local
838 	nv_mask(priv, 0x610200 + (chid * 0x10), 0x00000001, 0x00000000);  in nv50_disp_pioc_fini()
839 	if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00000000)) {  in nv50_disp_pioc_fini()
841 			 nv_rd32(priv, 0x610200 + (chid * 0x10)));  in nv50_disp_pioc_fini()
894 	.chid = 5,
942 	.chid = 7,
1326 nv50_disp_intr_error(struct nv50_disp_priv *priv, int chid)  in nv50_disp_intr_error()  argument
1329 	u32 data = nv_rd32(priv, 0x610084 + (chid * 0x08));  in nv50_disp_intr_error()
1330 	u32 addr = nv_rd32(priv, 0x610080 + (chid * 0x08));  in nv50_disp_intr_error()
1347 		 chid, mthd, data);  in nv50_disp_intr_error()
1349 	if (chid == 0) {  in nv50_disp_intr_error()
1352 			nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 0,  in nv50_disp_intr_error()
1359 	if (chid <= 2) {  in nv50_disp_intr_error()
1362 			nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 1,  in nv50_disp_intr_error()
1369 	if (chid <= 4) {  in nv50_disp_intr_error()
1372 			nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 3,  in nv50_disp_intr_error()
1380 	nv_wr32(priv, 0x610020, 0x00010000 << chid);  in nv50_disp_intr_error()
1381 	nv_wr32(priv, 0x610080 + (chid * 0x08), 0x90000000);  in nv50_disp_intr_error()
1932 		u32 chid = __ffs(intr0 & 0x001f0000) - 16;  in nv50_disp_intr()  local
1933 		nv50_disp_intr_error(priv, chid);  in nv50_disp_intr()
1934 		intr0 &= ~(0x00010000 << chid);  in nv50_disp_intr()
1938 		u32 chid = __ffs(intr0 & 0x0000001f);  in nv50_disp_intr()  local
1939 		nv50_disp_chan_uevent_send(priv, chid);  in nv50_disp_intr()
1940 		intr0 &= ~(0x00000001 << chid);  in nv50_disp_intr()