92 	struct nv_dma_v0 args = {};  in nouveau_channel_prep()  local
136 		args.target = NV_DMA_V0_TARGET_VM;  in nouveau_channel_prep()
137 		args.access = NV_DMA_V0_ACCESS_VM;  in nouveau_channel_prep()
138 		args.start = 0;  in nouveau_channel_prep()
139 		args.limit = cli->vm->mmu->limit - 1;  in nouveau_channel_prep()
147 			args.target = NV_DMA_V0_TARGET_PCI;  in nouveau_channel_prep()
148 			args.access = NV_DMA_V0_ACCESS_RDWR;  in nouveau_channel_prep()
149 			args.start = nv_device_resource_start(nvxx_device(device), 1);  in nouveau_channel_prep()
150 			args.limit = args.start + device->info.ram_user - 1;  in nouveau_channel_prep()
152 			args.target = NV_DMA_V0_TARGET_VRAM;  in nouveau_channel_prep()
153 			args.access = NV_DMA_V0_ACCESS_RDWR;  in nouveau_channel_prep()
154 			args.start = 0;  in nouveau_channel_prep()
155 			args.limit = device->info.ram_user - 1;  in nouveau_channel_prep()
159 			args.target = NV_DMA_V0_TARGET_AGP;  in nouveau_channel_prep()
160 			args.access = NV_DMA_V0_ACCESS_RDWR;  in nouveau_channel_prep()
161 			args.start = chan->drm->agp.base;  in nouveau_channel_prep()
162 			args.limit = chan->drm->agp.base +  in nouveau_channel_prep()
165 			args.target = NV_DMA_V0_TARGET_VM;  in nouveau_channel_prep()
166 			args.access = NV_DMA_V0_ACCESS_RDWR;  in nouveau_channel_prep()
167 			args.start = 0;  in nouveau_channel_prep()
168 			args.limit = mmu->limit - 1;  in nouveau_channel_prep()
174 			       &args, sizeof(args), &chan->push.ctxdma);  in nouveau_channel_prep()
197 	} args, *retn;  in nouveau_channel_ind()  local
211 			args.kepler.version = 0;  in nouveau_channel_ind()
212 			args.kepler.engine  = engine;  in nouveau_channel_ind()
213 			args.kepler.pushbuf = chan->push.ctxdma.handle;  in nouveau_channel_ind()
214 			args.kepler.ilength = 0x02000;  in nouveau_channel_ind()
215 			args.kepler.ioffset = 0x10000 + chan->push.vma.offset;  in nouveau_channel_ind()
216 			size = sizeof(args.kepler);  in nouveau_channel_ind()
218 			args.nv50.version = 0;  in nouveau_channel_ind()
219 			args.nv50.pushbuf = chan->push.ctxdma.handle;  in nouveau_channel_ind()
220 			args.nv50.ilength = 0x02000;  in nouveau_channel_ind()
221 			args.nv50.ioffset = 0x10000 + chan->push.vma.offset;  in nouveau_channel_ind()
222 			size = sizeof(args.nv50);  in nouveau_channel_ind()
226 				      &args, size, &chan->object);  in nouveau_channel_ind()
251 	struct nv03_channel_dma_v0 args, *retn;  in nouveau_channel_dma()  local
262 	args.version = 0;  in nouveau_channel_dma()
263 	args.pushbuf = chan->push.ctxdma.handle;  in nouveau_channel_dma()
264 	args.offset = chan->push.vma.offset;  in nouveau_channel_dma()
268 				      &args, sizeof(args), &chan->object);  in nouveau_channel_dma()
287 	struct nv_dma_v0 args = {};  in nouveau_channel_init()  local
295 			args.target = NV_DMA_V0_TARGET_VM;  in nouveau_channel_init()
296 			args.access = NV_DMA_V0_ACCESS_VM;  in nouveau_channel_init()
297 			args.start = 0;  in nouveau_channel_init()
298 			args.limit = cli->vm->mmu->limit - 1;  in nouveau_channel_init()
300 			args.target = NV_DMA_V0_TARGET_VRAM;  in nouveau_channel_init()
301 			args.access = NV_DMA_V0_ACCESS_RDWR;  in nouveau_channel_init()
302 			args.start = 0;  in nouveau_channel_init()
303 			args.limit = device->info.ram_user - 1;  in nouveau_channel_init()
307 				       NV_DMA_IN_MEMORY, &args,  in nouveau_channel_init()
308 				       sizeof(args), &chan->vram);  in nouveau_channel_init()
313 			args.target = NV_DMA_V0_TARGET_VM;  in nouveau_channel_init()
314 			args.access = NV_DMA_V0_ACCESS_VM;  in nouveau_channel_init()
315 			args.start = 0;  in nouveau_channel_init()
316 			args.limit = cli->vm->mmu->limit - 1;  in nouveau_channel_init()
319 			args.target = NV_DMA_V0_TARGET_AGP;  in nouveau_channel_init()
320 			args.access = NV_DMA_V0_ACCESS_RDWR;  in nouveau_channel_init()
321 			args.start = chan->drm->agp.base;  in nouveau_channel_init()
322 			args.limit = chan->drm->agp.base +  in nouveau_channel_init()
325 			args.target = NV_DMA_V0_TARGET_VM;  in nouveau_channel_init()
326 			args.access = NV_DMA_V0_ACCESS_RDWR;  in nouveau_channel_init()
327 			args.start = 0;  in nouveau_channel_init()
328 			args.limit = mmu->limit - 1;  in nouveau_channel_init()
332 				       NV_DMA_IN_MEMORY, &args,  in nouveau_channel_init()
333 				       sizeof(args), &chan->gart);  in nouveau_channel_init()