Lines Matching refs:fp_control
108 crtcstate[head].fp_control = FP_TG_CONTROL_OFF; in nv04_dfp_disable()
122 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control; in nv04_dfp_update_fp_control()
137 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control; in nv04_dfp_update_fp_control()
321 regp->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | in nv04_dfp_mode_set()
322 (savep->fp_control & (1 << 26 | NV_PRAMDAC_FP_TG_CONTROL_READ_PROG)); in nv04_dfp_mode_set()
326 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS; in nv04_dfp_mode_set()
328 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS; in nv04_dfp_mode_set()
332 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER; in nv04_dfp_mode_set()
335 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE; in nv04_dfp_mode_set()
337 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE; in nv04_dfp_mode_set()
339 regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12; in nv04_dfp_mode_set()
342 regp->fp_control |= (2 << 24); in nv04_dfp_mode_set()
354 regp->fp_control |= (8 << 28); in nv04_dfp_mode_set()
357 regp->fp_control |= (8 << 28); in nv04_dfp_mode_set()
462 nv04_display(dev)->mode_reg.crtc_reg[head].fp_control = in nv04_dfp_commit()