243 	struct drm_framebuffer *fb = crtc->primary->fb;  in nv_crtc_mode_set_vga()  local
377 	regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8;  in nv_crtc_mode_set_vga()
390 		XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);  in nv_crtc_mode_set_vga()
392 		XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);  in nv_crtc_mode_set_vga()
578 	regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->primary->fb->depth + 1) / 8;  in nv_crtc_mode_set_regs()
592 	if (crtc->primary->fb->depth == 16)  in nv_crtc_mode_set_regs()
613 	struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb);  in nv_crtc_swap_fbs()
812 	if (!nv_crtc->base.primary->fb) {  in nv_crtc_gamma_set()
830 	struct nouveau_framebuffer *fb;  in nv04_crtc_do_mode_set_base()  local
836 	if (!atomic && !crtc->primary->fb) {  in nv04_crtc_do_mode_set_base()
846 		fb = nouveau_framebuffer(passed_fb);  in nv04_crtc_do_mode_set_base()
848 		drm_fb = crtc->primary->fb;  in nv04_crtc_do_mode_set_base()
849 		fb = nouveau_framebuffer(crtc->primary->fb);  in nv04_crtc_do_mode_set_base()
852 	nv_crtc->fb.offset = fb->nvbo->bo.offset;  in nv04_crtc_do_mode_set_base()
861 	regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->primary->fb->depth + 1) / 8;  in nv04_crtc_do_mode_set_base()
863 	if (crtc->primary->fb->depth == 16)  in nv04_crtc_do_mode_set_base()
879 	regp->fb_start = nv_crtc->fb.offset & ~3;  in nv04_crtc_do_mode_set_base()
912 			       struct drm_framebuffer *fb,  in nv04_crtc_mode_set_base_atomic()  argument
923 	return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true);  in nv04_crtc_mode_set_base_atomic()