153 static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val)  in MDSS_HW_VERSION_STEP()
159 static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val)  in MDSS_HW_VERSION_MINOR()
165 static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val)  in MDSS_HW_VERSION_MAJOR()
177 static inline uint32_t __offset_MDP(uint32_t idx)  in __offset_MDP()
184 static inline uint32_t REG_MDP5_MDP(uint32_t i0) { return 0x00000000 + __offset_MDP(i0); }  in REG_MDP5_MDP()
186 static inline uint32_t REG_MDP5_MDP_HW_VERSION(uint32_t i0) { return 0x00000000 + __offset_MDP(i0);…  in REG_MDP5_MDP_HW_VERSION()
189 static inline uint32_t MDP5_MDP_HW_VERSION_STEP(uint32_t val)  in MDP5_MDP_HW_VERSION_STEP()
195 static inline uint32_t MDP5_MDP_HW_VERSION_MINOR(uint32_t val)  in MDP5_MDP_HW_VERSION_MINOR()
201 static inline uint32_t MDP5_MDP_HW_VERSION_MAJOR(uint32_t val)  in MDP5_MDP_HW_VERSION_MAJOR()
206 static inline uint32_t REG_MDP5_MDP_DISP_INTF_SEL(uint32_t i0) { return 0x00000004 + __offset_MDP(i…  in REG_MDP5_MDP_DISP_INTF_SEL()
209 static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val)  in MDP5_MDP_DISP_INTF_SEL_INTF0()
215 static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val)  in MDP5_MDP_DISP_INTF_SEL_INTF1()
221 static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val)  in MDP5_MDP_DISP_INTF_SEL_INTF2()
227 static inline uint32_t MDP5_MDP_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val)  in MDP5_MDP_DISP_INTF_SEL_INTF3()
232 static inline uint32_t REG_MDP5_MDP_INTR_EN(uint32_t i0) { return 0x00000010 + __offset_MDP(i0); }  in REG_MDP5_MDP_INTR_EN()
234 static inline uint32_t REG_MDP5_MDP_INTR_STATUS(uint32_t i0) { return 0x00000014 + __offset_MDP(i0)…  in REG_MDP5_MDP_INTR_STATUS()
236 static inline uint32_t REG_MDP5_MDP_INTR_CLEAR(uint32_t i0) { return 0x00000018 + __offset_MDP(i0);…  in REG_MDP5_MDP_INTR_CLEAR()
238 static inline uint32_t REG_MDP5_MDP_HIST_INTR_EN(uint32_t i0) { return 0x0000001c + __offset_MDP(i0…  in REG_MDP5_MDP_HIST_INTR_EN()
240 static inline uint32_t REG_MDP5_MDP_HIST_INTR_STATUS(uint32_t i0) { return 0x00000020 + __offset_MD…  in REG_MDP5_MDP_HIST_INTR_STATUS()
242 static inline uint32_t REG_MDP5_MDP_HIST_INTR_CLEAR(uint32_t i0) { return 0x00000024 + __offset_MDP…  in REG_MDP5_MDP_HIST_INTR_CLEAR()
244 static inline uint32_t REG_MDP5_MDP_SPARE_0(uint32_t i0) { return 0x00000028 + __offset_MDP(i0); }  in REG_MDP5_MDP_SPARE_0()
247 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W(uint32_t i0, uint32_t i1) { return 0x00000080 + __o…  in REG_MDP5_MDP_SMP_ALLOC_W()
249 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W_REG(uint32_t i0, uint32_t i1) { return 0x00000080 +…  in REG_MDP5_MDP_SMP_ALLOC_W_REG()
252 static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0(uint32_t val)  in MDP5_MDP_SMP_ALLOC_W_REG_CLIENT0()
258 static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1(uint32_t val)  in MDP5_MDP_SMP_ALLOC_W_REG_CLIENT1()
264 static inline uint32_t MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2(uint32_t val)  in MDP5_MDP_SMP_ALLOC_W_REG_CLIENT2()
269 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R(uint32_t i0, uint32_t i1) { return 0x00000130 + __o…  in REG_MDP5_MDP_SMP_ALLOC_R()
271 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R_REG(uint32_t i0, uint32_t i1) { return 0x00000130 +…  in REG_MDP5_MDP_SMP_ALLOC_R_REG()
274 static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0(uint32_t val)  in MDP5_MDP_SMP_ALLOC_R_REG_CLIENT0()
280 static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1(uint32_t val)  in MDP5_MDP_SMP_ALLOC_R_REG_CLIENT1()
286 static inline uint32_t MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2(uint32_t val)  in MDP5_MDP_SMP_ALLOC_R_REG_CLIENT2()
291 static inline uint32_t __offset_IGC(enum mdp5_igc_type idx)  in __offset_IGC()
301 static inline uint32_t REG_MDP5_MDP_IGC(uint32_t i0, enum mdp5_igc_type i1) { return 0x00000000 + _…  in REG_MDP5_MDP_IGC()
303 static inline uint32_t REG_MDP5_MDP_IGC_LUT(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { retu…  in REG_MDP5_MDP_IGC_LUT()
305 static inline uint32_t REG_MDP5_MDP_IGC_LUT_REG(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { …  in REG_MDP5_MDP_IGC_LUT_REG()
308 static inline uint32_t MDP5_MDP_IGC_LUT_REG_VAL(uint32_t val)  in MDP5_MDP_IGC_LUT_REG_VAL()
331 static inline uint32_t __offset_CTL(uint32_t idx)  in __offset_CTL()
342 static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); }  in REG_MDP5_CTL()
344 static inline uint32_t __offset_LAYER(uint32_t idx)  in __offset_LAYER()
356 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_…  in REG_MDP5_CTL_LAYER()
358 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __off…  in REG_MDP5_CTL_LAYER_REG()
361 static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(enum mdp_mixer_stage_id val)  in MDP5_CTL_LAYER_REG_VIG0()
367 static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(enum mdp_mixer_stage_id val)  in MDP5_CTL_LAYER_REG_VIG1()
373 static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(enum mdp_mixer_stage_id val)  in MDP5_CTL_LAYER_REG_VIG2()
379 static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(enum mdp_mixer_stage_id val)  in MDP5_CTL_LAYER_REG_RGB0()
385 static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(enum mdp_mixer_stage_id val)  in MDP5_CTL_LAYER_REG_RGB1()
391 static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(enum mdp_mixer_stage_id val)  in MDP5_CTL_LAYER_REG_RGB2()
397 static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(enum mdp_mixer_stage_id val)  in MDP5_CTL_LAYER_REG_DMA0()
403 static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(enum mdp_mixer_stage_id val)  in MDP5_CTL_LAYER_REG_DMA1()
411 static inline uint32_t MDP5_CTL_LAYER_REG_VIG3(enum mdp_mixer_stage_id val)  in MDP5_CTL_LAYER_REG_VIG3()
417 static inline uint32_t MDP5_CTL_LAYER_REG_RGB3(enum mdp_mixer_stage_id val)  in MDP5_CTL_LAYER_REG_RGB3()
422 static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); }  in REG_MDP5_CTL_OP()
425 static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val)  in MDP5_CTL_OP_MODE()
431 static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val)  in MDP5_CTL_OP_INTF_NUM()
439 static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val)  in MDP5_CTL_OP_PACK_3D()
444 static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); }  in REG_MDP5_CTL_FLUSH()
475 static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); }  in REG_MDP5_CTL_START()
477 static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); }  in REG_MDP5_CTL_PACK_3D()
479 static inline uint32_t __offset_PIPE(enum mdp5_pipe idx)  in __offset_PIPE()
495 static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); }  in REG_MDP5_PIPE()
497 static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE…  in REG_MDP5_PIPE_OP_MODE()
500 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(enum mdp5_data_format val)  in MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT()
506 static inline uint32_t MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(enum mdp5_data_format val)  in MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT()
512 static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offse…  in REG_MDP5_PIPE_HIST_CTL_BASE()
514 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offse…  in REG_MDP5_PIPE_HIST_LUT_BASE()
516 static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offse…  in REG_MDP5_PIPE_HIST_LUT_SWAP()
518 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0()
521 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11()
527 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12()
532 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1()
535 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13()
541 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21()
546 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2()
549 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22()
555 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23()
560 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3()
563 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31()
569 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32()
574 static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + …  in REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4()
577 static inline uint32_t MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(uint32_t val)  in MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33()
582 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x000…  in REG_MDP5_PIPE_CSC_1_PRE_CLAMP()
584 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0…  in REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG()
587 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(uint32_t val)  in MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH()
593 static inline uint32_t MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(uint32_t val)  in MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW()
598 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00…  in REG_MDP5_PIPE_CSC_1_POST_CLAMP()
600 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return …  in REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG()
603 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(uint32_t val)  in MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH()
609 static inline uint32_t MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(uint32_t val)  in MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW()
614 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000…  in REG_MDP5_PIPE_CSC_1_PRE_BIAS()
616 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x…  in REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG()
619 static inline uint32_t MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(uint32_t val)  in MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE()
624 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x000…  in REG_MDP5_PIPE_CSC_1_POST_BIAS()
626 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0…  in REG_MDP5_PIPE_CSC_1_POST_BIAS_REG()
629 static inline uint32_t MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(uint32_t val)  in MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE()
634 static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIP…  in REG_MDP5_PIPE_SRC_SIZE()
637 static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val)  in MDP5_PIPE_SRC_SIZE_HEIGHT()
643 static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val)  in MDP5_PIPE_SRC_SIZE_WIDTH()
648 static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset…  in REG_MDP5_PIPE_SRC_IMG_SIZE()
651 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val)  in MDP5_PIPE_SRC_IMG_SIZE_HEIGHT()
657 static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val)  in MDP5_PIPE_SRC_IMG_SIZE_WIDTH()
662 static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(…  in REG_MDP5_PIPE_SRC_XY()
665 static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val)  in MDP5_PIPE_SRC_XY_Y()
671 static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val)  in MDP5_PIPE_SRC_XY_X()
676 static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIP…  in REG_MDP5_PIPE_OUT_SIZE()
679 static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val)  in MDP5_PIPE_OUT_SIZE_HEIGHT()
685 static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val)  in MDP5_PIPE_OUT_SIZE_WIDTH()
690 static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(…  in REG_MDP5_PIPE_OUT_XY()
693 static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val)  in MDP5_PIPE_OUT_XY_Y()
699 static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val)  in MDP5_PIPE_OUT_XY_X()
704 static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PI…  in REG_MDP5_PIPE_SRC0_ADDR()
706 static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PI…  in REG_MDP5_PIPE_SRC1_ADDR()
708 static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PI…  in REG_MDP5_PIPE_SRC2_ADDR()
710 static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PI…  in REG_MDP5_PIPE_SRC3_ADDR()
712 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset…  in REG_MDP5_PIPE_SRC_STRIDE_A()
715 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val)  in MDP5_PIPE_SRC_STRIDE_A_P0()
721 static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val)  in MDP5_PIPE_SRC_STRIDE_A_P1()
726 static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset…  in REG_MDP5_PIPE_SRC_STRIDE_B()
729 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val)  in MDP5_PIPE_SRC_STRIDE_B_P2()
735 static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val)  in MDP5_PIPE_SRC_STRIDE_B_P3()
740 static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __of…  in REG_MDP5_PIPE_STILE_FRAME_SIZE()
742 static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_P…  in REG_MDP5_PIPE_SRC_FORMAT()
745 static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)  in MDP5_PIPE_SRC_FORMAT_G_BPC()
751 static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)  in MDP5_PIPE_SRC_FORMAT_B_BPC()
757 static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)  in MDP5_PIPE_SRC_FORMAT_R_BPC()
763 static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)  in MDP5_PIPE_SRC_FORMAT_A_BPC()
770 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val)  in MDP5_PIPE_SRC_FORMAT_CPP()
777 static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)  in MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT()
785 static inline uint32_t MDP5_PIPE_SRC_FORMAT_NUM_PLANES(enum mdp_sspp_fetch_type val)  in MDP5_PIPE_SRC_FORMAT_NUM_PLANES()
791 static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)  in MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP()
796 static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_P…  in REG_MDP5_PIPE_SRC_UNPACK()
799 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val)  in MDP5_PIPE_SRC_UNPACK_ELEM0()
805 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val)  in MDP5_PIPE_SRC_UNPACK_ELEM1()
811 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val)  in MDP5_PIPE_SRC_UNPACK_ELEM2()
817 static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val)  in MDP5_PIPE_SRC_UNPACK_ELEM3()
822 static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_…  in REG_MDP5_PIPE_SRC_OP_MODE()
826 static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val)  in MDP5_PIPE_SRC_OP_MODE_BWC()
838 static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __…  in REG_MDP5_PIPE_SRC_CONSTANT_COLOR()
840 static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset…  in REG_MDP5_PIPE_FETCH_CONFIG()
842 static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PI…  in REG_MDP5_PIPE_VC1_RANGE()
844 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __o…  in REG_MDP5_PIPE_REQPRIO_FIFO_WM_0()
846 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __o…  in REG_MDP5_PIPE_REQPRIO_FIFO_WM_1()
848 static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __o…  in REG_MDP5_PIPE_REQPRIO_FIFO_WM_2()
850 static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __…  in REG_MDP5_PIPE_SRC_ADDR_SW_STATUS()
852 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __o…  in REG_MDP5_PIPE_CURRENT_SRC0_ADDR()
854 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __o…  in REG_MDP5_PIPE_CURRENT_SRC1_ADDR()
856 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __o…  in REG_MDP5_PIPE_CURRENT_SRC2_ADDR()
858 static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __o…  in REG_MDP5_PIPE_CURRENT_SRC3_ADDR()
860 static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_P…  in REG_MDP5_PIPE_DECIMATION()
863 static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val)  in MDP5_PIPE_DECIMATION_VERT()
869 static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val)  in MDP5_PIPE_DECIMATION_HORZ()
874 static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset…  in REG_MDP5_PIPE_SCALE_CONFIG()
879 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER()
885 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER()
891 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER()
897 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER()
903 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER()
909 static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER(enum mdp5_scale_filter val)  in MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER()
914 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __…  in REG_MDP5_PIPE_SCALE_PHASE_STEP_X()
916 static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __…  in REG_MDP5_PIPE_SCALE_PHASE_STEP_Y()
918 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 +…  in REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X()
920 static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c +…  in REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y()
922 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __…  in REG_MDP5_PIPE_SCALE_INIT_PHASE_X()
924 static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __…  in REG_MDP5_PIPE_SCALE_INIT_PHASE_Y()
926 static inline uint32_t __offset_LM(uint32_t idx)  in __offset_LM()
938 static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); }  in REG_MDP5_LM()
940 static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i…  in REG_MDP5_LM_BLEND_COLOR_OUT()
946 static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); }  in REG_MDP5_LM_OUT_SIZE()
949 static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val)  in MDP5_LM_OUT_SIZE_HEIGHT()
955 static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val)  in MDP5_LM_OUT_SIZE_WIDTH()
960 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0…  in REG_MDP5_LM_BORDER_COLOR_0()
962 static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0…  in REG_MDP5_LM_BORDER_COLOR_1()
964 static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_L…  in REG_MDP5_LM_BLEND()
966 static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000020 + __…  in REG_MDP5_LM_BLEND_OP_MODE()
969 static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val)  in MDP5_LM_BLEND_OP_MODE_FG_ALPHA()
979 static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val)  in MDP5_LM_BLEND_OP_MODE_BG_ALPHA()
988 static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000024 + _…  in REG_MDP5_LM_BLEND_FG_ALPHA()
990 static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000028 + _…  in REG_MDP5_LM_BLEND_BG_ALPHA()
992 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP5_LM_BLEND_FG_TRANSP_LOW0()
994 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP5_LM_BLEND_FG_TRANSP_LOW1()
996 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0()
998 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1()
1000 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP5_LM_BLEND_BG_TRANSP_LOW0()
1002 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP5_LM_BLEND_BG_TRANSP_LOW1()
1004 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0()
1006 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000…  in REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1()
1008 static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i…  in REG_MDP5_LM_CURSOR_IMG_SIZE()
1011 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_W(uint32_t val)  in MDP5_LM_CURSOR_IMG_SIZE_SRC_W()
1017 static inline uint32_t MDP5_LM_CURSOR_IMG_SIZE_SRC_H(uint32_t val)  in MDP5_LM_CURSOR_IMG_SIZE_SRC_H()
1022 static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); }  in REG_MDP5_LM_CURSOR_SIZE()
1025 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_W(uint32_t val)  in MDP5_LM_CURSOR_SIZE_ROI_W()
1031 static inline uint32_t MDP5_LM_CURSOR_SIZE_ROI_H(uint32_t val)  in MDP5_LM_CURSOR_SIZE_ROI_H()
1036 static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); }  in REG_MDP5_LM_CURSOR_XY()
1039 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_X(uint32_t val)  in MDP5_LM_CURSOR_XY_SRC_X()
1045 static inline uint32_t MDP5_LM_CURSOR_XY_SRC_Y(uint32_t val)  in MDP5_LM_CURSOR_XY_SRC_Y()
1050 static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0)…  in REG_MDP5_LM_CURSOR_STRIDE()
1053 static inline uint32_t MDP5_LM_CURSOR_STRIDE_STRIDE(uint32_t val)  in MDP5_LM_CURSOR_STRIDE_STRIDE()
1058 static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0)…  in REG_MDP5_LM_CURSOR_FORMAT()
1061 static inline uint32_t MDP5_LM_CURSOR_FORMAT_FORMAT(enum mdp5_cursor_format val)  in MDP5_LM_CURSOR_FORMAT_FORMAT()
1066 static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(…  in REG_MDP5_LM_CURSOR_BASE_ADDR()
1068 static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i…  in REG_MDP5_LM_CURSOR_START_XY()
1071 static inline uint32_t MDP5_LM_CURSOR_START_XY_X_START(uint32_t val)  in MDP5_LM_CURSOR_START_XY_X_START()
1077 static inline uint32_t MDP5_LM_CURSOR_START_XY_Y_START(uint32_t val)  in MDP5_LM_CURSOR_START_XY_Y_START()
1082 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_…  in REG_MDP5_LM_CURSOR_BLEND_CONFIG()
1086 static inline uint32_t MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(enum mdp5_cursor_alpha val)  in MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL()
1092 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_L…  in REG_MDP5_LM_CURSOR_BLEND_PARAM()
1094 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __of…  in REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0()
1096 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __of…  in REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1()
1098 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __o…  in REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0()
1100 static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __o…  in REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1()
1102 static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); }  in REG_MDP5_LM_GC_LUT_BASE()
1104 static inline uint32_t __offset_DSPP(uint32_t idx)  in __offset_DSPP()
1114 static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }  in REG_MDP5_DSPP()
1116 static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); }  in REG_MDP5_DSPP_OP_MODE()
1120 static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val)  in MDP5_DSPP_OP_MODE_IGC_TBL_IDX()
1133 static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0);…  in REG_MDP5_DSPP_PCC_BASE()
1135 static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(…  in REG_MDP5_DSPP_DITHER_DEPTH()
1137 static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP…  in REG_MDP5_DSPP_HIST_CTL_BASE()
1139 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP…  in REG_MDP5_DSPP_HIST_LUT_BASE()
1141 static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP…  in REG_MDP5_DSPP_HIST_LUT_SWAP()
1143 static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); }  in REG_MDP5_DSPP_PA_BASE()
1145 static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0…  in REG_MDP5_DSPP_GAMUT_BASE()
1147 static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); }  in REG_MDP5_DSPP_GC_BASE()
1149 static inline uint32_t __offset_PP(uint32_t idx)  in __offset_PP()
1159 static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); }  in REG_MDP5_PP()
1161 static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0)…  in REG_MDP5_PP_TEAR_CHECK_EN()
1163 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP…  in REG_MDP5_PP_SYNC_CONFIG_VSYNC()
1166 static inline uint32_t MDP5_PP_SYNC_CONFIG_VSYNC_COUNT(uint32_t val)  in MDP5_PP_SYNC_CONFIG_VSYNC_COUNT()
1173 static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_P…  in REG_MDP5_PP_SYNC_CONFIG_HEIGHT()
1175 static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0);…  in REG_MDP5_PP_SYNC_WRCOUNT()
1178 static inline uint32_t MDP5_PP_SYNC_WRCOUNT_LINE_COUNT(uint32_t val)  in MDP5_PP_SYNC_WRCOUNT_LINE_COUNT()
1184 static inline uint32_t MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT(uint32_t val)  in MDP5_PP_SYNC_WRCOUNT_FRAME_COUNT()
1189 static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0…  in REG_MDP5_PP_VSYNC_INIT_VAL()
1191 static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0)…  in REG_MDP5_PP_INT_COUNT_VAL()
1194 static inline uint32_t MDP5_PP_INT_COUNT_VAL_LINE_COUNT(uint32_t val)  in MDP5_PP_INT_COUNT_VAL_LINE_COUNT()
1200 static inline uint32_t MDP5_PP_INT_COUNT_VAL_FRAME_COUNT(uint32_t val)  in MDP5_PP_INT_COUNT_VAL_FRAME_COUNT()
1205 static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); }  in REG_MDP5_PP_SYNC_THRESH()
1208 static inline uint32_t MDP5_PP_SYNC_THRESH_START(uint32_t val)  in MDP5_PP_SYNC_THRESH_START()
1214 static inline uint32_t MDP5_PP_SYNC_THRESH_CONTINUE(uint32_t val)  in MDP5_PP_SYNC_THRESH_CONTINUE()
1219 static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); }  in REG_MDP5_PP_START_POS()
1221 static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); }  in REG_MDP5_PP_RD_PTR_IRQ()
1223 static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); }  in REG_MDP5_PP_WR_PTR_IRQ()
1225 static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0…  in REG_MDP5_PP_OUT_LINE_COUNT()
1227 static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0)…  in REG_MDP5_PP_PP_LINE_COUNT()
1229 static inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_P…  in REG_MDP5_PP_AUTOREFRESH_CONFIG()
1231 static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); }  in REG_MDP5_PP_FBC_MODE()
1233 static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0…  in REG_MDP5_PP_FBC_BUDGET_CTL()
1235 static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0…  in REG_MDP5_PP_FBC_LOSSY_MODE()
1237 static inline uint32_t __offset_INTF(uint32_t idx)  in __offset_INTF()
1248 static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); }  in REG_MDP5_INTF()
1250 static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_I…  in REG_MDP5_INTF_TIMING_ENGINE_EN()
1252 static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); }  in REG_MDP5_INTF_CONFIG()
1254 static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0)…  in REG_MDP5_INTF_HSYNC_CTL()
1257 static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val)  in MDP5_INTF_HSYNC_CTL_PULSEW()
1263 static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val)  in MDP5_INTF_HSYNC_CTL_PERIOD()
1268 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_IN…  in REG_MDP5_INTF_VSYNC_PERIOD_F0()
1270 static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_IN…  in REG_MDP5_INTF_VSYNC_PERIOD_F1()
1272 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(…  in REG_MDP5_INTF_VSYNC_LEN_F0()
1274 static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(…  in REG_MDP5_INTF_VSYNC_LEN_F1()
1276 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_…  in REG_MDP5_INTF_DISPLAY_VSTART_F0()
1278 static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_…  in REG_MDP5_INTF_DISPLAY_VSTART_F1()
1280 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_IN…  in REG_MDP5_INTF_DISPLAY_VEND_F0()
1282 static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_IN…  in REG_MDP5_INTF_DISPLAY_VEND_F1()
1284 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_I…  in REG_MDP5_INTF_ACTIVE_VSTART_F0()
1287 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val)  in MDP5_INTF_ACTIVE_VSTART_F0_VAL()
1293 static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_I…  in REG_MDP5_INTF_ACTIVE_VSTART_F1()
1296 static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val)  in MDP5_INTF_ACTIVE_VSTART_F1_VAL()
1301 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INT…  in REG_MDP5_INTF_ACTIVE_VEND_F0()
1303 static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INT…  in REG_MDP5_INTF_ACTIVE_VEND_F1()
1305 static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(…  in REG_MDP5_INTF_DISPLAY_HCTL()
1308 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val)  in MDP5_INTF_DISPLAY_HCTL_START()
1314 static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val)  in MDP5_INTF_DISPLAY_HCTL_END()
1319 static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i…  in REG_MDP5_INTF_ACTIVE_HCTL()
1322 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val)  in MDP5_INTF_ACTIVE_HCTL_START()
1328 static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val)  in MDP5_INTF_ACTIVE_HCTL_END()
1334 static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(…  in REG_MDP5_INTF_BORDER_COLOR()
1336 static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_IN…  in REG_MDP5_INTF_UNDERFLOW_COLOR()
1338 static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0…  in REG_MDP5_INTF_HSYNC_SKEW()
1340 static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(…  in REG_MDP5_INTF_POLARITY_CTL()
1345 static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0);…  in REG_MDP5_INTF_TEST_CTL()
1347 static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0)…  in REG_MDP5_INTF_TP_COLOR0()
1349 static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0)…  in REG_MDP5_INTF_TP_COLOR1()
1351 static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __o…  in REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN()
1353 static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(…  in REG_MDP5_INTF_PANEL_FORMAT()
1355 static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offse…  in REG_MDP5_INTF_FRAME_LINE_COUNT_EN()
1357 static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i…  in REG_MDP5_INTF_FRAME_COUNT()
1359 static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0…  in REG_MDP5_INTF_LINE_COUNT()
1361 static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_I…  in REG_MDP5_INTF_DEFLICKER_CONFIG()
1363 static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __off…  in REG_MDP5_INTF_DEFLICKER_STRNG_COEFF()
1365 static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offs…  in REG_MDP5_INTF_DEFLICKER_WEAK_COEFF()
1367 static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0…  in REG_MDP5_INTF_TPG_ENABLE()
1369 static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_I…  in REG_MDP5_INTF_TPG_MAIN_CONTROL()
1371 static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_I…  in REG_MDP5_INTF_TPG_VIDEO_CONFIG()
1373 static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offs…  in REG_MDP5_INTF_TPG_COMPONENT_LIMITS()
1375 static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF…  in REG_MDP5_INTF_TPG_RECTANGLE()
1377 static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_…  in REG_MDP5_INTF_TPG_INITIAL_VALUE()
1379 static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 +…  in REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME()
1381 static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_IN…  in REG_MDP5_INTF_TPG_RGB_MAPPING()
1383 static inline uint32_t __offset_AD(uint32_t idx)  in __offset_AD()
1391 static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }  in REG_MDP5_AD()
1393 static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); }  in REG_MDP5_AD_BYPASS()
1395 static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); }  in REG_MDP5_AD_CTRL_0()
1397 static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); }  in REG_MDP5_AD_CTRL_1()
1399 static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); }  in REG_MDP5_AD_FRAME_SIZE()
1401 static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); }  in REG_MDP5_AD_CON_CTRL_0()
1403 static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); }  in REG_MDP5_AD_CON_CTRL_1()
1405 static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); }  in REG_MDP5_AD_STR_MAN()
1407 static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); }  in REG_MDP5_AD_VAR()
1409 static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); }  in REG_MDP5_AD_DITH()
1411 static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); }  in REG_MDP5_AD_DITH_CTRL()
1413 static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); }  in REG_MDP5_AD_AMP_LIM()
1415 static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); }  in REG_MDP5_AD_SLOPE()
1417 static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); }  in REG_MDP5_AD_BW_LVL()
1419 static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); }  in REG_MDP5_AD_LOGO_POS()
1421 static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); }  in REG_MDP5_AD_LUT_FI()
1423 static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); }  in REG_MDP5_AD_LUT_CC()
1425 static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); }  in REG_MDP5_AD_STR_LIM()
1427 static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); }  in REG_MDP5_AD_CALIB_AB()
1429 static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); }  in REG_MDP5_AD_CALIB_CD()
1431 static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); }  in REG_MDP5_AD_MODE_SEL()
1433 static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); }  in REG_MDP5_AD_TFILT_CTRL()
1435 static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); }  in REG_MDP5_AD_BL_MINMAX()
1437 static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); }  in REG_MDP5_AD_BL()
1439 static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); }  in REG_MDP5_AD_BL_MAX()
1441 static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); }  in REG_MDP5_AD_AL()
1443 static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); }  in REG_MDP5_AD_AL_MIN()
1445 static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); }  in REG_MDP5_AD_AL_FILT()
1447 static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); }  in REG_MDP5_AD_CFG_BUF()
1449 static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); }  in REG_MDP5_AD_LUT_AL()
1451 static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); }  in REG_MDP5_AD_TARG_STR()
1453 static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); }  in REG_MDP5_AD_START_CALC()
1455 static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); }  in REG_MDP5_AD_STR_OUT()
1457 static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); }  in REG_MDP5_AD_BL_OUT()
1459 static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); }  in REG_MDP5_AD_CALC_DONE()