112 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val)  in MDP4_VERSION_MINOR()
118 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val)  in MDP4_VERSION_MAJOR()
140 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val)  in MDP4_DISP_INTF_SEL_PRIM()
146 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val)  in MDP4_DISP_INTF_SEL_SEC()
152 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)  in MDP4_DISP_INTF_SEL_EXT()
182 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE0()
189 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE1()
196 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE2()
203 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE3()
210 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE4()
217 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE5()
224 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE6()
231 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE7()
242 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE0()
249 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE1()
256 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE2()
263 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE3()
270 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE4()
277 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE5()
284 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE6()
291 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE7()
309 static inline uint32_t __offset_OVLP(uint32_t idx)  in __offset_OVLP()
318 static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); }  in REG_MDP4_OVLP()
320 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); }  in REG_MDP4_OVLP_CFG()
322 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); }  in REG_MDP4_OVLP_SIZE()
325 static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val)  in MDP4_OVLP_SIZE_HEIGHT()
331 static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val)  in MDP4_OVLP_SIZE_WIDTH()
336 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); }  in REG_MDP4_OVLP_BASE()
338 static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); }  in REG_MDP4_OVLP_STRIDE()
340 static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); }  in REG_MDP4_OVLP_OPMODE()
342 static inline uint32_t __offset_STAGE(uint32_t idx)  in __offset_STAGE()
352 static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset…  in REG_MDP4_OVLP_STAGE()
354 static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __off…  in REG_MDP4_OVLP_STAGE_OP()
357 static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val)  in MDP4_OVLP_STAGE_OP_FG_ALPHA()
365 static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val)  in MDP4_OVLP_STAGE_OP_BG_ALPHA()
374 static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 +…  in REG_MDP4_OVLP_STAGE_FG_ALPHA()
376 static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 +…  in REG_MDP4_OVLP_STAGE_BG_ALPHA()
378 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000…  in REG_MDP4_OVLP_STAGE_TRANSP_LOW0()
380 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x0000001…  in REG_MDP4_OVLP_STAGE_TRANSP_LOW1()
382 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP4_OVLP_STAGE_TRANSP_HIGH0()
384 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x000000…  in REG_MDP4_OVLP_STAGE_TRANSP_HIGH1()
386 static inline uint32_t __offset_STAGE_CO3(uint32_t idx)  in __offset_STAGE_CO3()
396 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __of…  in REG_MDP4_OVLP_STAGE_CO3()
398 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + …  in REG_MDP4_OVLP_STAGE_CO3_SEL()
401 static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i…  in REG_MDP4_OVLP_TRANSP_LOW0()
403 static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i…  in REG_MDP4_OVLP_TRANSP_LOW1()
405 static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(…  in REG_MDP4_OVLP_TRANSP_HIGH0()
407 static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(…  in REG_MDP4_OVLP_TRANSP_HIGH1()
409 static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0…  in REG_MDP4_OVLP_CSC_CONFIG()
411 static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); }  in REG_MDP4_OVLP_CSC()
414 static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offse…  in REG_MDP4_OVLP_CSC_MV()
416 static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __o…  in REG_MDP4_OVLP_CSC_MV_VAL()
418 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __o…  in REG_MDP4_OVLP_CSC_PRE_BV()
420 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 +…  in REG_MDP4_OVLP_CSC_PRE_BV_VAL()
422 static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __…  in REG_MDP4_OVLP_CSC_POST_BV()
424 static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 …  in REG_MDP4_OVLP_CSC_POST_BV_VAL()
426 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __o…  in REG_MDP4_OVLP_CSC_PRE_LV()
428 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 +…  in REG_MDP4_OVLP_CSC_PRE_LV_VAL()
430 static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __…  in REG_MDP4_OVLP_CSC_POST_LV()
432 static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 …  in REG_MDP4_OVLP_CSC_POST_LV_VAL()
436 static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; }  in REG_MDP4_LUTN()
438 static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 +…  in REG_MDP4_LUTN_LUT()
440 static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*…  in REG_MDP4_LUTN_LUT_VAL()
444 static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; }  in REG_MDP4_DMA_E_QUANT()
446 static inline uint32_t __offset_DMA(enum mdp4_dma idx)  in __offset_DMA()
455 static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); }  in REG_MDP4_DMA()
457 static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0)…  in REG_MDP4_DMA_CONFIG()
460 static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val)  in MDP4_DMA_CONFIG_G_BPC()
466 static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val)  in MDP4_DMA_CONFIG_B_BPC()
472 static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val)  in MDP4_DMA_CONFIG_R_BPC()
479 static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val)  in MDP4_DMA_CONFIG_PACK()
486 static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i…  in REG_MDP4_DMA_SRC_SIZE()
489 static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val)  in MDP4_DMA_SRC_SIZE_HEIGHT()
495 static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val)  in MDP4_DMA_SRC_SIZE_WIDTH()
500 static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i…  in REG_MDP4_DMA_SRC_BASE()
502 static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA…  in REG_MDP4_DMA_SRC_STRIDE()
504 static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i…  in REG_MDP4_DMA_DST_SIZE()
507 static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val)  in MDP4_DMA_DST_SIZE_HEIGHT()
513 static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val)  in MDP4_DMA_DST_SIZE_WIDTH()
518 static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DM…  in REG_MDP4_DMA_CURSOR_SIZE()
521 static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val)  in MDP4_DMA_CURSOR_SIZE_WIDTH()
527 static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val)  in MDP4_DMA_CURSOR_SIZE_HEIGHT()
532 static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DM…  in REG_MDP4_DMA_CURSOR_BASE()
534 static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA…  in REG_MDP4_DMA_CURSOR_POS()
537 static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val)  in MDP4_DMA_CURSOR_POS_X()
543 static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val)  in MDP4_DMA_CURSOR_POS_Y()
548 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __o…  in REG_MDP4_DMA_CURSOR_BLEND_CONFIG()
552 static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val)  in MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT()
558 static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __of…  in REG_MDP4_DMA_CURSOR_BLEND_PARAM()
560 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offse…  in REG_MDP4_DMA_BLEND_TRANS_LOW()
562 static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offs…  in REG_MDP4_DMA_BLEND_TRANS_HIGH()
564 static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_D…  in REG_MDP4_DMA_FETCH_CONFIG()
566 static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); }  in REG_MDP4_DMA_CSC()
569 static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __o…  in REG_MDP4_DMA_CSC_MV()
571 static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 +…  in REG_MDP4_DMA_CSC_MV_VAL()
573 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 +…  in REG_MDP4_DMA_CSC_PRE_BV()
575 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x000035…  in REG_MDP4_DMA_CSC_PRE_BV_VAL()
577 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 …  in REG_MDP4_DMA_CSC_POST_BV()
579 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003…  in REG_MDP4_DMA_CSC_POST_BV_VAL()
581 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 +…  in REG_MDP4_DMA_CSC_PRE_LV()
583 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x000036…  in REG_MDP4_DMA_CSC_PRE_LV_VAL()
585 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 …  in REG_MDP4_DMA_CSC_POST_LV()
587 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003…  in REG_MDP4_DMA_CSC_POST_LV_VAL()
589 static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }  in REG_MDP4_PIPE()
591 static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; }  in REG_MDP4_PIPE_SRC_SIZE()
594 static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val)  in MDP4_PIPE_SRC_SIZE_HEIGHT()
600 static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val)  in MDP4_PIPE_SRC_SIZE_WIDTH()
605 static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; }  in REG_MDP4_PIPE_SRC_XY()
608 static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val)  in MDP4_PIPE_SRC_XY_Y()
614 static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val)  in MDP4_PIPE_SRC_XY_X()
619 static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; }  in REG_MDP4_PIPE_DST_SIZE()
622 static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val)  in MDP4_PIPE_DST_SIZE_HEIGHT()
628 static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val)  in MDP4_PIPE_DST_SIZE_WIDTH()
633 static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; }  in REG_MDP4_PIPE_DST_XY()
636 static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val)  in MDP4_PIPE_DST_XY_Y()
642 static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val)  in MDP4_PIPE_DST_XY_X()
647 static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0…  in REG_MDP4_PIPE_SRCP0_BASE()
649 static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0…  in REG_MDP4_PIPE_SRCP1_BASE()
651 static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0…  in REG_MDP4_PIPE_SRCP2_BASE()
653 static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0…  in REG_MDP4_PIPE_SRCP3_BASE()
655 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*…  in REG_MDP4_PIPE_SRC_STRIDE_A()
658 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val)  in MDP4_PIPE_SRC_STRIDE_A_P0()
664 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val)  in MDP4_PIPE_SRC_STRIDE_A_P1()
669 static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*…  in REG_MDP4_PIPE_SRC_STRIDE_B()
672 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val)  in MDP4_PIPE_SRC_STRIDE_B_P2()
678 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val)  in MDP4_PIPE_SRC_STRIDE_B_P3()
683 static inline uint32_t REG_MDP4_PIPE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0…  in REG_MDP4_PIPE_FRAME_SIZE()
686 static inline uint32_t MDP4_PIPE_FRAME_SIZE_HEIGHT(uint32_t val)  in MDP4_PIPE_FRAME_SIZE_HEIGHT()
692 static inline uint32_t MDP4_PIPE_FRAME_SIZE_WIDTH(uint32_t val)  in MDP4_PIPE_FRAME_SIZE_WIDTH()
697 static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0…  in REG_MDP4_PIPE_SRC_FORMAT()
700 static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)  in MDP4_PIPE_SRC_FORMAT_G_BPC()
706 static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)  in MDP4_PIPE_SRC_FORMAT_B_BPC()
712 static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)  in MDP4_PIPE_SRC_FORMAT_R_BPC()
718 static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)  in MDP4_PIPE_SRC_FORMAT_A_BPC()
725 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val)  in MDP4_PIPE_SRC_FORMAT_CPP()
732 static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)  in MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT()
740 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val)  in MDP4_PIPE_SRC_FORMAT_FETCH_PLANES()
747 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)  in MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP()
753 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val)  in MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT()
758 static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0…  in REG_MDP4_PIPE_SRC_UNPACK()
761 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val)  in MDP4_PIPE_SRC_UNPACK_ELEM0()
767 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val)  in MDP4_PIPE_SRC_UNPACK_ELEM1()
773 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val)  in MDP4_PIPE_SRC_UNPACK_ELEM2()
779 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val)  in MDP4_PIPE_SRC_UNPACK_ELEM3()
784 static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; }  in REG_MDP4_PIPE_OP_MODE()
789 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val)  in MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL()
795 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val)  in MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL()
809 static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i…  in REG_MDP4_PIPE_PHASEX_STEP()
811 static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i…  in REG_MDP4_PIPE_PHASEY_STEP()
813 static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*…  in REG_MDP4_PIPE_FETCH_CONFIG()
815 static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i…  in REG_MDP4_PIPE_SOLID_COLOR()
817 static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; }  in REG_MDP4_PIPE_CSC()
820 static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0…  in REG_MDP4_PIPE_CSC_MV()
822 static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400…  in REG_MDP4_PIPE_CSC_MV_VAL()
824 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500…  in REG_MDP4_PIPE_CSC_PRE_BV()
826 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x0002…  in REG_MDP4_PIPE_CSC_PRE_BV_VAL()
828 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x0002458…  in REG_MDP4_PIPE_CSC_POST_BV()
830 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x000…  in REG_MDP4_PIPE_CSC_POST_BV_VAL()
832 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600…  in REG_MDP4_PIPE_CSC_PRE_LV()
834 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x0002…  in REG_MDP4_PIPE_CSC_PRE_LV_VAL()
836 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x0002468…  in REG_MDP4_PIPE_CSC_POST_LV()
838 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x000…  in REG_MDP4_PIPE_CSC_POST_LV_VAL()
847 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val)  in MDP4_LCDC_HSYNC_CTRL_PULSEW()
853 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val)  in MDP4_LCDC_HSYNC_CTRL_PERIOD()
865 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val)  in MDP4_LCDC_DISPLAY_HCTRL_START()
871 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val)  in MDP4_LCDC_DISPLAY_HCTRL_END()
883 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val)  in MDP4_LCDC_ACTIVE_HCTL_START()
889 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val)  in MDP4_LCDC_ACTIVE_HCTL_END()
904 static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val)  in MDP4_LCDC_UNDERFLOW_CLR_COLOR()
937 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) { return 0x000c2014 + 0x8*i0; }  in REG_MDP4_LCDC_LVDS_MUX_CTL()
939 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { return 0x000c2014 + 0x8*i0;…  in REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0()
942 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0()
948 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1()
954 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2()
960 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3()
965 static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { return 0x000c2018 + 0x8*i0;…  in REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4()
968 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4()
974 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5()
980 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6()
1021 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val)  in MDP4_DTV_HSYNC_CTRL_PULSEW()
1027 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val)  in MDP4_DTV_HSYNC_CTRL_PERIOD()
1039 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val)  in MDP4_DTV_DISPLAY_HCTRL_START()
1045 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val)  in MDP4_DTV_DISPLAY_HCTRL_END()
1057 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val)  in MDP4_DTV_ACTIVE_HCTL_START()
1063 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val)  in MDP4_DTV_ACTIVE_HCTL_END()
1078 static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val)  in MDP4_DTV_UNDERFLOW_CLR_COLOR()
1100 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val)  in MDP4_DSI_HSYNC_CTRL_PULSEW()
1106 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val)  in MDP4_DSI_HSYNC_CTRL_PERIOD()
1118 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val)  in MDP4_DSI_DISPLAY_HCTRL_START()
1124 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val)  in MDP4_DSI_DISPLAY_HCTRL_END()
1136 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val)  in MDP4_DSI_ACTIVE_HCTL_START()
1142 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val)  in MDP4_DSI_ACTIVE_HCTL_END()
1157 static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val)  in MDP4_DSI_UNDERFLOW_CLR_COLOR()