110 	u8 lane_cnt;  member
457 	ctrl->lane_cnt = lane;  in edp_fill_link_cfg()
458 	DBG("rate=%d lane=%d", ctrl->link_rate, ctrl->lane_cnt);  in edp_fill_link_cfg()
466 	data = EDP_CONFIGURATION_CTRL_LANES(ctrl->lane_cnt - 1);  in edp_config_ctrl()
541 	for (i = 0; i < ctrl->lane_cnt; i++) {  in edp_sink_train_set_adjust()
552 	for (i = 0; i < ctrl->lane_cnt; i++) {  in edp_sink_train_set_adjust()
645 		if (drm_dp_clock_recovery_ok(link_status, ctrl->lane_cnt)) {  in edp_start_link_train_1()
702 		if (drm_dp_channel_eq_ok(link_status, ctrl->lane_cnt)) {  in edp_start_link_train_2()
729 	lane = ctrl->lane_cnt;  in edp_link_rate_down_shift()
758 			ctrl->lane_cnt = lane;  in edp_link_rate_down_shift()
788 	dp_link.num_lanes = ctrl->lane_cnt;  in edp_do_link_train()
928 		msm_edp_phy_lane_power_ctrl(ctrl->phy, true, ctrl->lane_cnt);  in edp_ctrl_link_enable()