716 	WREG_CRT(0x0d, (u8)(addr & 0xff));  in mga_set_start_address()
717 	WREG_CRT(0x0c, (u8)(addr >> 8) & 0xff);  in mga_set_start_address()
930 	WREG_CRT(0, htotal - 4);  in mga_crtc_mode_set()
931 	WREG_CRT(1, hdisplay);  in mga_crtc_mode_set()
932 	WREG_CRT(2, hdisplay);  in mga_crtc_mode_set()
933 	WREG_CRT(3, (htotal & 0x1F) | 0x80);  in mga_crtc_mode_set()
934 	WREG_CRT(4, hsyncstart);  in mga_crtc_mode_set()
935 	WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));  in mga_crtc_mode_set()
936 	WREG_CRT(6, vtotal & 0xFF);  in mga_crtc_mode_set()
937 	WREG_CRT(7, ((vtotal & 0x100) >> 8) |  in mga_crtc_mode_set()
945 	WREG_CRT(9, ((vdisplay & 0x200) >> 4) |  in mga_crtc_mode_set()
947 	WREG_CRT(10, 0);  in mga_crtc_mode_set()
948 	WREG_CRT(11, 0);  in mga_crtc_mode_set()
949 	WREG_CRT(12, 0);  in mga_crtc_mode_set()
950 	WREG_CRT(13, 0);  in mga_crtc_mode_set()
951 	WREG_CRT(14, 0);  in mga_crtc_mode_set()
952 	WREG_CRT(15, 0);  in mga_crtc_mode_set()
953 	WREG_CRT(16, vsyncstart & 0xFF);  in mga_crtc_mode_set()
954 	WREG_CRT(17, (vsyncend & 0x0F) | 0x20);  in mga_crtc_mode_set()
955 	WREG_CRT(18, vdisplay & 0xFF);  in mga_crtc_mode_set()
956 	WREG_CRT(19, pitch & 0xFF);  in mga_crtc_mode_set()
957 	WREG_CRT(20, 0);  in mga_crtc_mode_set()
958 	WREG_CRT(21, vdisplay & 0xFF);  in mga_crtc_mode_set()
959 	WREG_CRT(22, (vtotal + 1) & 0xFF);  in mga_crtc_mode_set()
960 	WREG_CRT(23, 0xc3);  in mga_crtc_mode_set()
961 	WREG_CRT(24, vdisplay & 0xFF);  in mga_crtc_mode_set()
1195 	WREG_CRT(0x11, tmp | 0x80);  in mga_crtc_prepare()
1214 	WREG_CRT(17, 0);  in mga_crtc_prepare()