Lines Matching refs:pipe
625 enum pipe pipe; in vlv_dpio_cmn_power_well_disable() local
629 for_each_pipe(dev_priv, pipe) in vlv_dpio_cmn_power_well_disable()
630 assert_pll_disabled(dev_priv, pipe); in vlv_dpio_cmn_power_well_disable()
699 enum pipe pipe = power_well->data; in chv_pipe_power_well_enabled() local
705 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); in chv_pipe_power_well_enabled()
710 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); in chv_pipe_power_well_enabled()
711 enabled = state == DP_SSS_PWR_ON(pipe); in chv_pipe_power_well_enabled()
717 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); in chv_pipe_power_well_enabled()
729 enum pipe pipe = power_well->data; in chv_set_pipe_power_well() local
733 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); in chv_set_pipe_power_well()
738 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) in chv_set_pipe_power_well()
744 ctrl &= ~DP_SSC_MASK(pipe); in chv_set_pipe_power_well()
745 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); in chv_set_pipe_power_well()