70 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,  in hsw_power_well_enabled()  argument
89 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,  in __intel_display_power_is_enabled()  argument
97 	if (dev_priv->pm.suspended)  in __intel_display_power_is_enabled()
100 	power_domains = &dev_priv->power_domains;  in __intel_display_power_is_enabled()
134 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,  in intel_display_power_is_enabled()  argument
140 	power_domains = &dev_priv->power_domains;  in intel_display_power_is_enabled()
143 	ret = __intel_display_power_is_enabled(dev_priv, domain);  in intel_display_power_is_enabled()
159 void intel_display_set_init_power(struct drm_i915_private *dev_priv,  in intel_display_set_init_power()  argument
162 	if (dev_priv->power_domains.init_power_on == enable)  in intel_display_set_init_power()
166 		intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);  in intel_display_set_init_power()
168 		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);  in intel_display_set_init_power()
170 	dev_priv->power_domains.init_power_on = enable;  in intel_display_set_init_power()
179 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)  in hsw_power_well_post_enable()  argument
181 	struct drm_device *dev = dev_priv->dev;  in hsw_power_well_post_enable()
198 		gen8_irq_power_well_post_enable(dev_priv,  in hsw_power_well_post_enable()
202 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,  in skl_power_well_post_enable()  argument
205 	struct drm_device *dev = dev_priv->dev;  in skl_power_well_post_enable()
222 		gen8_irq_power_well_post_enable(dev_priv,  in skl_power_well_post_enable()
228 		gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);  in skl_power_well_post_enable()
232 static void hsw_set_power_well(struct drm_i915_private *dev_priv,  in hsw_set_power_well()  argument
252 			hsw_power_well_post_enable(dev_priv);  in hsw_set_power_well()
322 static void skl_set_power_well(struct drm_i915_private *dev_priv,  in skl_set_power_well()  argument
396 		skl_power_well_post_enable(dev_priv, power_well);  in skl_set_power_well()
399 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,  in hsw_power_well_sync_hw()  argument
402 	hsw_set_power_well(dev_priv, power_well, power_well->count > 0);  in hsw_power_well_sync_hw()
412 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,  in hsw_power_well_enable()  argument
415 	hsw_set_power_well(dev_priv, power_well, true);  in hsw_power_well_enable()
418 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,  in hsw_power_well_disable()  argument
421 	hsw_set_power_well(dev_priv, power_well, false);  in hsw_power_well_disable()
424 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,  in skl_power_well_enabled()  argument
433 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,  in skl_power_well_sync_hw()  argument
436 	skl_set_power_well(dev_priv, power_well, power_well->count > 0);  in skl_power_well_sync_hw()
442 static void skl_power_well_enable(struct drm_i915_private *dev_priv,  in skl_power_well_enable()  argument
445 	skl_set_power_well(dev_priv, power_well, true);  in skl_power_well_enable()
448 static void skl_power_well_disable(struct drm_i915_private *dev_priv,  in skl_power_well_disable()  argument
451 	skl_set_power_well(dev_priv, power_well, false);  in skl_power_well_disable()
454 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,  in i9xx_always_on_power_well_noop()  argument
459 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,  in i9xx_always_on_power_well_enabled()  argument
465 static void vlv_set_power_well(struct drm_i915_private *dev_priv,  in vlv_set_power_well()  argument
477 	mutex_lock(&dev_priv->rps.hw_lock);  in vlv_set_power_well()
480 	((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)  in vlv_set_power_well()
485 	ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);  in vlv_set_power_well()
488 	vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);  in vlv_set_power_well()
493 			  vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));  in vlv_set_power_well()
498 	mutex_unlock(&dev_priv->rps.hw_lock);  in vlv_set_power_well()
501 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,  in vlv_power_well_sync_hw()  argument
504 	vlv_set_power_well(dev_priv, power_well, power_well->count > 0);  in vlv_power_well_sync_hw()
507 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,  in vlv_power_well_enable()  argument
510 	vlv_set_power_well(dev_priv, power_well, true);  in vlv_power_well_enable()
513 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,  in vlv_power_well_disable()  argument
516 	vlv_set_power_well(dev_priv, power_well, false);  in vlv_power_well_disable()
519 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,  in vlv_power_well_enabled()  argument
531 	mutex_lock(&dev_priv->rps.hw_lock);  in vlv_power_well_enabled()
533 	state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;  in vlv_power_well_enabled()
547 	ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;  in vlv_power_well_enabled()
550 	mutex_unlock(&dev_priv->rps.hw_lock);  in vlv_power_well_enabled()
555 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,  in vlv_display_power_well_enable()  argument
560 	vlv_set_power_well(dev_priv, power_well, true);  in vlv_display_power_well_enable()
562 	spin_lock_irq(&dev_priv->irq_lock);  in vlv_display_power_well_enable()
563 	valleyview_enable_display_irqs(dev_priv);  in vlv_display_power_well_enable()
564 	spin_unlock_irq(&dev_priv->irq_lock);  in vlv_display_power_well_enable()
570 	if (dev_priv->power_domains.initializing)  in vlv_display_power_well_enable()
573 	intel_hpd_init(dev_priv);  in vlv_display_power_well_enable()
575 	i915_redisable_vga_power_on(dev_priv->dev);  in vlv_display_power_well_enable()
578 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,  in vlv_display_power_well_disable()  argument
583 	spin_lock_irq(&dev_priv->irq_lock);  in vlv_display_power_well_disable()
584 	valleyview_disable_display_irqs(dev_priv);  in vlv_display_power_well_disable()
585 	spin_unlock_irq(&dev_priv->irq_lock);  in vlv_display_power_well_disable()
587 	vlv_set_power_well(dev_priv, power_well, false);  in vlv_display_power_well_disable()
589 	vlv_power_sequencer_reset(dev_priv);  in vlv_display_power_well_disable()
592 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,  in vlv_dpio_cmn_power_well_enable()  argument
606 	vlv_set_power_well(dev_priv, power_well, true);  in vlv_dpio_cmn_power_well_enable()
622 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,  in vlv_dpio_cmn_power_well_disable()  argument
629 	for_each_pipe(dev_priv, pipe)  in vlv_dpio_cmn_power_well_disable()
630 		assert_pll_disabled(dev_priv, pipe);  in vlv_dpio_cmn_power_well_disable()
635 	vlv_set_power_well(dev_priv, power_well, false);  in vlv_dpio_cmn_power_well_disable()
638 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,  in chv_dpio_cmn_power_well_enable()  argument
663 	vlv_set_power_well(dev_priv, power_well, true);  in chv_dpio_cmn_power_well_enable()
673 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,  in chv_dpio_cmn_power_well_disable()  argument
683 		assert_pll_disabled(dev_priv, PIPE_A);  in chv_dpio_cmn_power_well_disable()
684 		assert_pll_disabled(dev_priv, PIPE_B);  in chv_dpio_cmn_power_well_disable()
687 		assert_pll_disabled(dev_priv, PIPE_C);  in chv_dpio_cmn_power_well_disable()
693 	vlv_set_power_well(dev_priv, power_well, false);  in chv_dpio_cmn_power_well_disable()
696 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,  in chv_pipe_power_well_enabled()  argument
703 	mutex_lock(&dev_priv->rps.hw_lock);  in chv_pipe_power_well_enabled()
705 	state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);  in chv_pipe_power_well_enabled()
717 	ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);  in chv_pipe_power_well_enabled()
720 	mutex_unlock(&dev_priv->rps.hw_lock);  in chv_pipe_power_well_enabled()
725 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,  in chv_set_pipe_power_well()  argument
735 	mutex_lock(&dev_priv->rps.hw_lock);  in chv_set_pipe_power_well()
738 	((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)  in chv_set_pipe_power_well()
743 	ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);  in chv_set_pipe_power_well()
746 	vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);  in chv_set_pipe_power_well()
751 			  vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));  in chv_set_pipe_power_well()
756 	mutex_unlock(&dev_priv->rps.hw_lock);  in chv_set_pipe_power_well()
759 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,  in chv_pipe_power_well_sync_hw()  argument
762 	chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);  in chv_pipe_power_well_sync_hw()
765 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,  in chv_pipe_power_well_enable()  argument
772 	chv_set_pipe_power_well(dev_priv, power_well, true);  in chv_pipe_power_well_enable()
775 		spin_lock_irq(&dev_priv->irq_lock);  in chv_pipe_power_well_enable()
776 		valleyview_enable_display_irqs(dev_priv);  in chv_pipe_power_well_enable()
777 		spin_unlock_irq(&dev_priv->irq_lock);  in chv_pipe_power_well_enable()
783 		if (dev_priv->power_domains.initializing)  in chv_pipe_power_well_enable()
786 		intel_hpd_init(dev_priv);  in chv_pipe_power_well_enable()
788 		i915_redisable_vga_power_on(dev_priv->dev);  in chv_pipe_power_well_enable()
792 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,  in chv_pipe_power_well_disable()  argument
800 		spin_lock_irq(&dev_priv->irq_lock);  in chv_pipe_power_well_disable()
801 		valleyview_disable_display_irqs(dev_priv);  in chv_pipe_power_well_disable()
802 		spin_unlock_irq(&dev_priv->irq_lock);  in chv_pipe_power_well_disable()
805 	chv_set_pipe_power_well(dev_priv, power_well, false);  in chv_pipe_power_well_disable()
808 		vlv_power_sequencer_reset(dev_priv);  in chv_pipe_power_well_disable()
823 void intel_display_power_get(struct drm_i915_private *dev_priv,  in intel_display_power_get()  argument
830 	intel_runtime_pm_get(dev_priv);  in intel_display_power_get()
832 	power_domains = &dev_priv->power_domains;  in intel_display_power_get()
839 			power_well->ops->enable(dev_priv, power_well);  in intel_display_power_get()
858 void intel_display_power_put(struct drm_i915_private *dev_priv,  in intel_display_power_put()  argument
865 	power_domains = &dev_priv->power_domains;  in intel_display_power_put()
878 			power_well->ops->disable(dev_priv, power_well);  in intel_display_power_put()
884 	intel_runtime_pm_put(dev_priv);  in intel_display_power_put()
1250 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,  in lookup_power_well()  argument
1253 	struct i915_power_domains *power_domains = &dev_priv->power_domains;  in lookup_power_well()
1328 int intel_power_domains_init(struct drm_i915_private *dev_priv)  in intel_power_domains_init()  argument
1330 	struct i915_power_domains *power_domains = &dev_priv->power_domains;  in intel_power_domains_init()
1338 	if (IS_HASWELL(dev_priv->dev)) {  in intel_power_domains_init()
1340 	} else if (IS_BROADWELL(dev_priv->dev)) {  in intel_power_domains_init()
1342 	} else if (IS_SKYLAKE(dev_priv->dev)) {  in intel_power_domains_init()
1344 	} else if (IS_CHERRYVIEW(dev_priv->dev)) {  in intel_power_domains_init()
1346 	} else if (IS_VALLEYVIEW(dev_priv->dev)) {  in intel_power_domains_init()
1355 static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv)  in intel_runtime_pm_disable()  argument
1357 	struct drm_device *dev = dev_priv->dev;  in intel_runtime_pm_disable()
1379 void intel_power_domains_fini(struct drm_i915_private *dev_priv)  in intel_power_domains_fini()  argument
1381 	intel_runtime_pm_disable(dev_priv);  in intel_power_domains_fini()
1386 	intel_display_set_init_power(dev_priv, true);  in intel_power_domains_fini()
1389 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)  in intel_power_domains_resume()  argument
1391 	struct i915_power_domains *power_domains = &dev_priv->power_domains;  in intel_power_domains_resume()
1397 		power_well->ops->sync_hw(dev_priv, power_well);  in intel_power_domains_resume()
1398 		power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,  in intel_power_domains_resume()
1404 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)  in vlv_cmnlane_wa()  argument
1407 		lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);  in vlv_cmnlane_wa()
1409 		lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);  in vlv_cmnlane_wa()
1412 	if (cmn->ops->is_enabled(dev_priv, cmn) &&  in vlv_cmnlane_wa()
1413 	    disp2d->ops->is_enabled(dev_priv, disp2d) &&  in vlv_cmnlane_wa()
1420 	disp2d->ops->enable(dev_priv, disp2d);  in vlv_cmnlane_wa()
1429 	cmn->ops->disable(dev_priv, cmn);  in vlv_cmnlane_wa()
1439 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)  in intel_power_domains_init_hw()  argument
1441 	struct drm_device *dev = dev_priv->dev;  in intel_power_domains_init_hw()
1442 	struct i915_power_domains *power_domains = &dev_priv->power_domains;  in intel_power_domains_init_hw()
1448 		vlv_cmnlane_wa(dev_priv);  in intel_power_domains_init_hw()
1453 	intel_display_set_init_power(dev_priv, true);  in intel_power_domains_init_hw()
1454 	intel_power_domains_resume(dev_priv);  in intel_power_domains_init_hw()
1470 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)  in intel_aux_display_runtime_get()  argument
1472 	intel_runtime_pm_get(dev_priv);  in intel_aux_display_runtime_get()
1483 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)  in intel_aux_display_runtime_put()  argument
1485 	intel_runtime_pm_put(dev_priv);  in intel_aux_display_runtime_put()
1498 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)  in intel_runtime_pm_get()  argument
1500 	struct drm_device *dev = dev_priv->dev;  in intel_runtime_pm_get()
1507 	WARN(dev_priv->pm.suspended, "Device still suspended.\n");  in intel_runtime_pm_get()
1527 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)  in intel_runtime_pm_get_noresume()  argument
1529 	struct drm_device *dev = dev_priv->dev;  in intel_runtime_pm_get_noresume()
1535 	WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");  in intel_runtime_pm_get_noresume()
1547 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)  in intel_runtime_pm_put()  argument
1549 	struct drm_device *dev = dev_priv->dev;  in intel_runtime_pm_put()
1569 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)  in intel_runtime_pm_enable()  argument
1571 	struct drm_device *dev = dev_priv->dev;  in intel_runtime_pm_enable()