1121 static int gen8_rcs_signal(struct intel_engine_cs *signaller,  in gen8_rcs_signal()  argument
1125 	struct drm_device *dev = signaller->dev;  in gen8_rcs_signal()
1134 	ret = intel_ring_begin(signaller, num_dwords);  in gen8_rcs_signal()
1140 		u64 gtt_offset = signaller->semaphore.signal_ggtt[i];  in gen8_rcs_signal()
1145 					   signaller->outstanding_lazy_request);  in gen8_rcs_signal()
1146 		intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));  in gen8_rcs_signal()
1147 		intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |  in gen8_rcs_signal()
1150 		intel_ring_emit(signaller, lower_32_bits(gtt_offset));  in gen8_rcs_signal()
1151 		intel_ring_emit(signaller, upper_32_bits(gtt_offset));  in gen8_rcs_signal()
1152 		intel_ring_emit(signaller, seqno);  in gen8_rcs_signal()
1153 		intel_ring_emit(signaller, 0);  in gen8_rcs_signal()
1154 		intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |  in gen8_rcs_signal()
1156 		intel_ring_emit(signaller, 0);  in gen8_rcs_signal()
1162 static int gen8_xcs_signal(struct intel_engine_cs *signaller,  in gen8_xcs_signal()  argument
1166 	struct drm_device *dev = signaller->dev;  in gen8_xcs_signal()
1175 	ret = intel_ring_begin(signaller, num_dwords);  in gen8_xcs_signal()
1181 		u64 gtt_offset = signaller->semaphore.signal_ggtt[i];  in gen8_xcs_signal()
1186 					   signaller->outstanding_lazy_request);  in gen8_xcs_signal()
1187 		intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |  in gen8_xcs_signal()
1189 		intel_ring_emit(signaller, lower_32_bits(gtt_offset) |  in gen8_xcs_signal()
1191 		intel_ring_emit(signaller, upper_32_bits(gtt_offset));  in gen8_xcs_signal()
1192 		intel_ring_emit(signaller, seqno);  in gen8_xcs_signal()
1193 		intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |  in gen8_xcs_signal()
1195 		intel_ring_emit(signaller, 0);  in gen8_xcs_signal()
1201 static int gen6_signal(struct intel_engine_cs *signaller,  in gen6_signal()  argument
1204 	struct drm_device *dev = signaller->dev;  in gen6_signal()
1214 	ret = intel_ring_begin(signaller, num_dwords);  in gen6_signal()
1219 		u32 mbox_reg = signaller->semaphore.mbox.signal[i];  in gen6_signal()
1222 					   signaller->outstanding_lazy_request);  in gen6_signal()
1223 			intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));  in gen6_signal()
1224 			intel_ring_emit(signaller, mbox_reg);  in gen6_signal()
1225 			intel_ring_emit(signaller, seqno);  in gen6_signal()
1231 		intel_ring_emit(signaller, MI_NOOP);  in gen6_signal()
1285 	       struct intel_engine_cs *signaller,  in gen8_ring_sync()  argument
1301 			lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));  in gen8_ring_sync()
1303 			upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));  in gen8_ring_sync()
1310 	       struct intel_engine_cs *signaller,  in gen6_ring_sync()  argument
1316 	u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];  in gen6_ring_sync()