217 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;  in intel_emit_post_sync_nonzero_flush()  local
228 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */  in intel_emit_post_sync_nonzero_flush()
240 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */  in intel_emit_post_sync_nonzero_flush()
254 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;  in gen6_render_ring_flush()  local
294 	intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);  in gen6_render_ring_flush()
325 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;  in gen7_render_ring_flush()  local
375 	intel_ring_emit(ring, scratch_addr);  in gen7_render_ring_flush()
384 		       u32 flags, u32 scratch_addr)  in gen8_emit_pipe_control()  argument
394 	intel_ring_emit(ring, scratch_addr);  in gen8_emit_pipe_control()
408 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;  in gen8_render_ring_flush()  local
437 	return gen8_emit_pipe_control(ring, flags, scratch_addr);  in gen8_render_ring_flush()
1360 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;  in pc_render_add_request()  local
1382 	PIPE_CONTROL_FLUSH(ring, scratch_addr);  in pc_render_add_request()
1383 	scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */  in pc_render_add_request()
1384 	PIPE_CONTROL_FLUSH(ring, scratch_addr);  in pc_render_add_request()
1385 	scratch_addr += 2 * CACHELINE_BYTES;  in pc_render_add_request()
1386 	PIPE_CONTROL_FLUSH(ring, scratch_addr);  in pc_render_add_request()
1387 	scratch_addr += 2 * CACHELINE_BYTES;  in pc_render_add_request()
1388 	PIPE_CONTROL_FLUSH(ring, scratch_addr);  in pc_render_add_request()
1389 	scratch_addr += 2 * CACHELINE_BYTES;  in pc_render_add_request()
1390 	PIPE_CONTROL_FLUSH(ring, scratch_addr);  in pc_render_add_request()
1391 	scratch_addr += 2 * CACHELINE_BYTES;  in pc_render_add_request()
1392 	PIPE_CONTROL_FLUSH(ring, scratch_addr);  in pc_render_add_request()