217 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;  in intel_emit_post_sync_nonzero_flush()
254 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;  in gen6_render_ring_flush()
325 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;  in gen7_render_ring_flush()
408 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;  in gen8_render_ring_flush()
689 	ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);  in intel_init_pipe_control()
697 			 ring->name, ring->scratch.gtt_offset);  in intel_init_pipe_control()
1140 		u64 gtt_offset = signaller->semaphore.signal_ggtt[i];  in gen8_rcs_signal()  local
1141 		if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)  in gen8_rcs_signal()
1150 		intel_ring_emit(signaller, lower_32_bits(gtt_offset));  in gen8_rcs_signal()
1151 		intel_ring_emit(signaller, upper_32_bits(gtt_offset));  in gen8_rcs_signal()
1181 		u64 gtt_offset = signaller->semaphore.signal_ggtt[i];  in gen8_xcs_signal()  local
1182 		if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)  in gen8_xcs_signal()
1189 		intel_ring_emit(signaller, lower_32_bits(gtt_offset) |  in gen8_xcs_signal()
1191 		intel_ring_emit(signaller, upper_32_bits(gtt_offset));  in gen8_xcs_signal()
1360 	u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;  in pc_render_add_request()
1378 	intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);  in pc_render_add_request()
1398 	intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);  in pc_render_add_request()
1741 	u32 cs_offset = ring->scratch.gtt_offset;  in i830_dispatch_execbuffer()
2622 		ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);  in intel_init_render_ring_buffer()