Lines Matching refs:I915_WRITE
471 I915_WRITE(HWS_PGA, addr); in ring_setup_phys_status_page()
510 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); in intel_ring_setup_status_page()
526 I915_WRITE(reg, in intel_ring_setup_status_page()
1065 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); in init_render_ring()
1074 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); in init_render_ring()
1079 I915_WRITE(GFX_MODE, in init_render_ring()
1084 I915_WRITE(GFX_MODE_GEN7, in init_render_ring()
1094 I915_WRITE(CACHE_MODE_0, in init_render_ring()
1099 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); in init_render_ring()
1489 I915_WRITE(IMR, dev_priv->irq_mask); in i9xx_ring_get_irq()
1507 I915_WRITE(IMR, dev_priv->irq_mask); in i9xx_ring_put_irq()
2290 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); in intel_ring_init_seqno()
2291 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); in intel_ring_init_seqno()
2293 I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); in intel_ring_init_seqno()
2310 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, in gen6_bsd_ring_write_tail()
2329 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, in gen6_bsd_ring_write_tail()