Lines Matching refs:I915_WRITE
90 I915_WRITE(ctl_reg, 0); in intel_psr_write_vsc()
95 I915_WRITE(data_reg + i, *data++); in intel_psr_write_vsc()
97 I915_WRITE(data_reg + i, 0); in intel_psr_write_vsc()
100 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); in intel_psr_write_vsc()
117 I915_WRITE(VLV_VSCSDP(pipe), val); in vlv_psr_setup_vsc()
175 I915_WRITE(aux_data_reg + i, in hsw_psr_enable_sink()
188 I915_WRITE(aux_ctl_reg, val); in hsw_psr_enable_sink()
190 I915_WRITE(aux_ctl_reg, in hsw_psr_enable_sink()
207 I915_WRITE(VLV_PSRCTL(pipe), in vlv_psr_enable_source()
226 I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) | in vlv_psr_activate()
253 I915_WRITE(EDP_PSR_CTL(dev), val | in hsw_psr_enable_source()
368 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | in intel_psr_enable()
415 I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val); in vlv_psr_disable()
430 I915_WRITE(EDP_PSR_CTL(dev), in hsw_psr_disable()
534 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE); in intel_psr_exit()
546 I915_WRITE(VLV_PSRCTL(pipe), val); in intel_psr_exit()