578 					const struct intel_watermark_params *wm,  in intel_calculate_wm()  argument
593 	entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);  in intel_calculate_wm()
597 	wm_size = fifo_size - (entries_required + wm->guard_size);  in intel_calculate_wm()
602 	if (wm_size > (long)wm->max_wm)  in intel_calculate_wm()
603 		wm_size = wm->max_wm;  in intel_calculate_wm()
605 		wm_size = wm->default_wm;  in intel_calculate_wm()
642 	unsigned long wm;  in pineview_update_wm()  local
662 		wm = intel_calculate_wm(clock, &pineview_display_wm,  in pineview_update_wm()
667 		reg |= FW_WM(wm, SR);  in pineview_update_wm()
672 		wm = intel_calculate_wm(clock, &pineview_cursor_wm,  in pineview_update_wm()
677 		reg |= FW_WM(wm, CURSOR_SR);  in pineview_update_wm()
681 		wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,  in pineview_update_wm()
686 		reg |= FW_WM(wm, HPLL_SR);  in pineview_update_wm()
690 		wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,  in pineview_update_wm()
695 		reg |= FW_WM(wm, HPLL_CURSOR);  in pineview_update_wm()
845 				const struct vlv_wm_values *wm)  in vlv_write_wm_values()  argument
851 		   (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |  in vlv_write_wm_values()
852 		   (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |  in vlv_write_wm_values()
853 		   (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |  in vlv_write_wm_values()
854 		   (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));  in vlv_write_wm_values()
857 		   FW_WM(wm->sr.plane, SR) |  in vlv_write_wm_values()
858 		   FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |  in vlv_write_wm_values()
859 		   FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |  in vlv_write_wm_values()
860 		   FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));  in vlv_write_wm_values()
862 		   FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |  in vlv_write_wm_values()
863 		   FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |  in vlv_write_wm_values()
864 		   FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));  in vlv_write_wm_values()
866 		   FW_WM(wm->sr.cursor, CURSOR_SR));  in vlv_write_wm_values()
870 			   FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |  in vlv_write_wm_values()
871 			   FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));  in vlv_write_wm_values()
873 			   FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |  in vlv_write_wm_values()
874 			   FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));  in vlv_write_wm_values()
876 			   FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |  in vlv_write_wm_values()
877 			   FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));  in vlv_write_wm_values()
879 			   FW_WM(wm->sr.plane >> 9, SR_HI) |  in vlv_write_wm_values()
880 			   FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |  in vlv_write_wm_values()
881 			   FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |  in vlv_write_wm_values()
882 			   FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |  in vlv_write_wm_values()
883 			   FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |  in vlv_write_wm_values()
884 			   FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |  in vlv_write_wm_values()
885 			   FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |  in vlv_write_wm_values()
886 			   FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |  in vlv_write_wm_values()
887 			   FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |  in vlv_write_wm_values()
888 			   FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));  in vlv_write_wm_values()
891 			   FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |  in vlv_write_wm_values()
892 			   FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));  in vlv_write_wm_values()
894 			   FW_WM(wm->sr.plane >> 9, SR_HI) |  in vlv_write_wm_values()
895 			   FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |  in vlv_write_wm_values()
896 			   FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |  in vlv_write_wm_values()
897 			   FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |  in vlv_write_wm_values()
898 			   FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |  in vlv_write_wm_values()
899 			   FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |  in vlv_write_wm_values()
900 			   FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));  in vlv_write_wm_values()
905 	dev_priv->wm.vlv = *wm;  in vlv_write_wm_values()
982 			      struct vlv_wm_values *wm)  in vlv_compute_sr_wm()  argument
991 	wm->sr.cursor = wm->sr.plane = 0;  in vlv_compute_sr_wm()
997 		num_planes = !!wm->pipe[pipe].primary +  in vlv_compute_sr_wm()
998 			!!wm->pipe[pipe].sprite[0] +  in vlv_compute_sr_wm()
999 			!!wm->pipe[pipe].sprite[1];  in vlv_compute_sr_wm()
1006 	wm->sr.cursor = vlv_compute_wm(to_intel_crtc(crtc),  in vlv_compute_sr_wm()
1016 		wm->sr.plane = vlv_compute_wm(to_intel_crtc(crtc),  in vlv_compute_sr_wm()
1018 		if (wm->sr.plane != 0)  in vlv_compute_sr_wm()
1032 	struct vlv_wm_values wm = dev_priv->wm.vlv;  in valleyview_update_wm()  local
1034 	wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);  in valleyview_update_wm()
1035 	wm.pipe[pipe].primary = vlv_compute_wm(intel_crtc,  in valleyview_update_wm()
1039 	wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);  in valleyview_update_wm()
1040 	wm.pipe[pipe].cursor = vlv_compute_wm(intel_crtc,  in valleyview_update_wm()
1044 	cxsr_enabled = vlv_compute_sr_wm(dev, &wm);  in valleyview_update_wm()
1046 	if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)  in valleyview_update_wm()
1051 		      wm.pipe[pipe].primary, wm.pipe[pipe].cursor,  in valleyview_update_wm()
1052 		      wm.sr.plane, wm.sr.cursor);  in valleyview_update_wm()
1068 	vlv_write_wm_values(intel_crtc, &wm);  in valleyview_update_wm()
1087 	struct vlv_wm_values wm = dev_priv->wm.vlv;  in valleyview_update_sprite_wm()  local
1090 		wm.ddl[pipe].sprite[sprite] =  in valleyview_update_sprite_wm()
1093 		wm.pipe[pipe].sprite[sprite] =  in valleyview_update_sprite_wm()
1098 		wm.ddl[pipe].sprite[sprite] = 0;  in valleyview_update_sprite_wm()
1099 		wm.pipe[pipe].sprite[sprite] = 0;  in valleyview_update_sprite_wm()
1102 	cxsr_enabled = vlv_compute_sr_wm(dev, &wm);  in valleyview_update_sprite_wm()
1104 	if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)  in valleyview_update_sprite_wm()
1110 		      wm.pipe[pipe].sprite[sprite],  in valleyview_update_sprite_wm()
1111 		      wm.sr.plane, wm.sr.cursor);  in valleyview_update_sprite_wm()
1116 	vlv_write_wm_values(intel_crtc, &wm);  in valleyview_update_sprite_wm()
1760 	uint16_t pri_latency = dev_priv->wm.pri_latency[level];  in ilk_compute_wm_level()
1761 	uint16_t spr_latency = dev_priv->wm.spr_latency[level];  in ilk_compute_wm_level()
1762 	uint16_t cur_latency = dev_priv->wm.cur_latency[level];  in ilk_compute_wm_level()
1801 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])  in intel_read_wm_latency()
1823 		wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;  in intel_read_wm_latency()
1824 		wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &  in intel_read_wm_latency()
1826 		wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &  in intel_read_wm_latency()
1828 		wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &  in intel_read_wm_latency()
1843 		wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;  in intel_read_wm_latency()
1844 		wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &  in intel_read_wm_latency()
1846 		wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &  in intel_read_wm_latency()
1848 		wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &  in intel_read_wm_latency()
1868 		wm[0] += 2;  in intel_read_wm_latency()
1870 			if (wm[level] != 0)  in intel_read_wm_latency()
1871 				wm[level] += 2;  in intel_read_wm_latency()
1874 					wm[i] = 0;  in intel_read_wm_latency()
1881 		wm[0] = (sskpd >> 56) & 0xFF;  in intel_read_wm_latency()
1882 		if (wm[0] == 0)  in intel_read_wm_latency()
1883 			wm[0] = sskpd & 0xF;  in intel_read_wm_latency()
1884 		wm[1] = (sskpd >> 4) & 0xFF;  in intel_read_wm_latency()
1885 		wm[2] = (sskpd >> 12) & 0xFF;  in intel_read_wm_latency()
1886 		wm[3] = (sskpd >> 20) & 0x1FF;  in intel_read_wm_latency()
1887 		wm[4] = (sskpd >> 32) & 0x1FF;  in intel_read_wm_latency()
1891 		wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;  in intel_read_wm_latency()
1892 		wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;  in intel_read_wm_latency()
1893 		wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;  in intel_read_wm_latency()
1894 		wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;  in intel_read_wm_latency()
1899 		wm[0] = 7;  in intel_read_wm_latency()
1900 		wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;  in intel_read_wm_latency()
1901 		wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;  in intel_read_wm_latency()
1905 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])  in intel_fixup_spr_wm_latency()
1909 		wm[0] = 13;  in intel_fixup_spr_wm_latency()
1912 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])  in intel_fixup_cur_wm_latency()
1916 		wm[0] = 13;  in intel_fixup_cur_wm_latency()
1920 		wm[3] *= 2;  in intel_fixup_cur_wm_latency()
1938 				   const uint16_t wm[8])  in intel_print_wm_latency()
1943 		unsigned int latency = wm[level];  in intel_print_wm_latency()
1961 			      name, level, wm[level],  in intel_print_wm_latency()
1967 				    uint16_t wm[5], uint16_t min)  in ilk_increase_wm_latency()
1971 	if (wm[0] >= min)  in ilk_increase_wm_latency()
1974 	wm[0] = max(wm[0], min);  in ilk_increase_wm_latency()
1976 		wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));  in ilk_increase_wm_latency()
1990 	changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |  in snb_wm_latency_quirk()
1991 		ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |  in snb_wm_latency_quirk()
1992 		ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);  in snb_wm_latency_quirk()
1998 	intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);  in snb_wm_latency_quirk()
1999 	intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);  in snb_wm_latency_quirk()
2000 	intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);  in snb_wm_latency_quirk()
2007 	intel_read_wm_latency(dev, dev_priv->wm.pri_latency);  in ilk_setup_wm_latency()
2009 	memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,  in ilk_setup_wm_latency()
2010 	       sizeof(dev_priv->wm.pri_latency));  in ilk_setup_wm_latency()
2011 	memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,  in ilk_setup_wm_latency()
2012 	       sizeof(dev_priv->wm.pri_latency));  in ilk_setup_wm_latency()
2014 	intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);  in ilk_setup_wm_latency()
2015 	intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);  in ilk_setup_wm_latency()
2017 	intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);  in ilk_setup_wm_latency()
2018 	intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);  in ilk_setup_wm_latency()
2019 	intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);  in ilk_setup_wm_latency()
2029 	intel_read_wm_latency(dev, dev_priv->wm.skl_latency);  in skl_setup_wm_latency()
2030 	intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);  in skl_setup_wm_latency()
2069 			p->spr = intel_plane->wm;  in ilk_compute_wm_parameters()
2082 		const struct intel_pipe_wm *wm = &intel_crtc->wm.active;  in ilk_compute_wm_config()  local
2084 		if (!wm->pipe_enabled)  in ilk_compute_wm_config()
2087 		config->sprites_enabled |= wm->sprites_enabled;  in ilk_compute_wm_config()
2088 		config->sprites_scaled |= wm->sprites_scaled;  in ilk_compute_wm_config()
2121 	ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);  in intel_compute_pipe_wm()
2130 	if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))  in intel_compute_pipe_wm()
2136 		struct intel_wm_level wm = {};  in intel_compute_pipe_wm()  local
2138 		ilk_compute_wm_level(dev_priv, level, params, &wm);  in intel_compute_pipe_wm()
2145 		if (!ilk_validate_wm_level(level, &max, &wm))  in intel_compute_pipe_wm()
2148 		pipe_wm->wm[level] = wm;  in intel_compute_pipe_wm()
2166 		const struct intel_pipe_wm *active = &intel_crtc->wm.active;  in ilk_merge_wm_level()
2167 		const struct intel_wm_level *wm = &active->wm[level];  in ilk_merge_wm_level()  local
2177 		if (!wm->enable)  in ilk_merge_wm_level()
2180 		ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);  in ilk_merge_wm_level()
2181 		ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);  in ilk_merge_wm_level()
2182 		ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);  in ilk_merge_wm_level()
2183 		ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);  in ilk_merge_wm_level()
2208 		struct intel_wm_level *wm = &merged->wm[level];  in ilk_wm_merge()  local
2210 		ilk_merge_wm_level(dev, level, wm);  in ilk_wm_merge()
2213 			wm->enable = false;  in ilk_wm_merge()
2214 		else if (!ilk_validate_wm_level(level, max, wm))  in ilk_wm_merge()
2222 		if (wm->fbc_val > max->fbc) {  in ilk_wm_merge()
2223 			if (wm->enable)  in ilk_wm_merge()
2225 			wm->fbc_val = 0;  in ilk_wm_merge()
2237 			struct intel_wm_level *wm = &merged->wm[level];  in ilk_wm_merge()  local
2239 			wm->enable = false;  in ilk_wm_merge()
2247 	return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);  in ilk_wm_lp_to_level()
2258 		return dev_priv->wm.pri_latency[level];  in ilk_wm_lp_latency()
2278 		r = &merged->wm[level];  in ilk_compute_wm_results()
2314 			&intel_crtc->wm.active.wm[0];  in ilk_compute_wm_results()
2319 		results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;  in ilk_compute_wm_results()
2338 		if (r1->wm[level].enable)  in ilk_find_best_result()
2340 		if (r2->wm[level].enable)  in ilk_find_best_result()
2419 	struct ilk_wm_values *previous = &dev_priv->wm.hw;  in _ilk_disable_lp_wm()
2454 	struct ilk_wm_values *previous = &dev_priv->wm.hw;  in ilk_write_wm_values()
2523 	dev_priv->wm.hw = *results;  in ilk_write_wm_values()
2782 	const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;  in skl_ddb_allocation_changed()
2809 		config->sprites_enabled |= intel_plane->wm.enabled;  in skl_compute_wm_global_parameters()
2810 		config->sprites_scaled |= intel_plane->wm.scaled;  in skl_compute_wm_global_parameters()
2862 			p->plane[i++] = intel_plane->wm;  in skl_compute_wm_pipe_parameters()
2874 	uint32_t latency = dev_priv->wm.skl_latency[level];  in skl_compute_plane_wm()
3010 				     &pipe_wm->wm[level]);  in skl_compute_pipe_wm()
3032 			temp |= p_wm->wm[level].plane_res_l[i] <<  in skl_compute_wm_results()
3034 			temp |= p_wm->wm[level].plane_res_b[i];  in skl_compute_wm_results()
3035 			if (p_wm->wm[level].plane_en[i])  in skl_compute_wm_results()
3043 		temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;  in skl_compute_wm_results()
3044 		temp |= p_wm->wm[level].cursor_res_b;  in skl_compute_wm_results()
3046 		if (p_wm->wm[level].cursor_en)  in skl_compute_wm_results()
3184 	cur_ddb = &dev_priv->wm.skl_hw.ddb;  in skl_flush_wm_values()
3268 	if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))  in skl_update_pipe_wm()
3271 	intel_crtc->wm.skl_active = *pipe_wm;  in skl_update_pipe_wm()
3330 	struct skl_wm_values *results = &dev_priv->wm.skl_results;  in skl_update_wm()
3350 	dev_priv->wm.skl_hw = *results;  in skl_update_wm()
3361 	intel_plane->wm.enabled = enabled;  in skl_update_sprite_wm()
3362 	intel_plane->wm.scaled = scaled;  in skl_update_sprite_wm()
3363 	intel_plane->wm.horiz_pixels = sprite_width;  in skl_update_sprite_wm()
3364 	intel_plane->wm.vert_pixels = sprite_height;  in skl_update_sprite_wm()
3365 	intel_plane->wm.bytes_per_pixel = pixel_size;  in skl_update_sprite_wm()
3366 	intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;  in skl_update_sprite_wm()
3372 		intel_plane->wm.tiling = fb->modifier[0];  in skl_update_sprite_wm()
3373 	intel_plane->wm.rotation = plane->state->rotation;  in skl_update_sprite_wm()
3395 	if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))  in ilk_update_wm()
3398 	intel_crtc->wm.active = pipe_wm;  in ilk_update_wm()
3433 	intel_plane->wm.enabled = enabled;  in ilk_update_sprite_wm()
3434 	intel_plane->wm.scaled = scaled;  in ilk_update_sprite_wm()
3435 	intel_plane->wm.horiz_pixels = sprite_width;  in ilk_update_sprite_wm()
3436 	intel_plane->wm.vert_pixels = sprite_width;  in ilk_update_sprite_wm()
3437 	intel_plane->wm.bytes_per_pixel = pixel_size;  in ilk_update_sprite_wm()
3463 			active->wm[level].plane_en[i] = is_enabled;  in skl_pipe_wm_active_state()
3464 			active->wm[level].plane_res_b[i] =  in skl_pipe_wm_active_state()
3466 			active->wm[level].plane_res_l[i] =  in skl_pipe_wm_active_state()
3470 			active->wm[level].cursor_en = is_enabled;  in skl_pipe_wm_active_state()
3471 			active->wm[level].cursor_res_b =  in skl_pipe_wm_active_state()
3473 			active->wm[level].cursor_res_l =  in skl_pipe_wm_active_state()
3500 	struct skl_wm_values *hw = &dev_priv->wm.skl_hw;  in skl_pipe_wm_get_hw_state()
3502 	struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;  in skl_pipe_wm_get_hw_state()
3551 	struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;  in skl_wm_get_hw_state()
3563 	struct ilk_wm_values *hw = &dev_priv->wm.hw;  in ilk_pipe_wm_get_hw_state()
3565 	struct intel_pipe_wm *active = &intel_crtc->wm.active;  in ilk_pipe_wm_get_hw_state()
3590 		active->wm[0].enable = true;  in ilk_pipe_wm_get_hw_state()
3591 		active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;  in ilk_pipe_wm_get_hw_state()
3592 		active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;  in ilk_pipe_wm_get_hw_state()
3593 		active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;  in ilk_pipe_wm_get_hw_state()
3604 			active->wm[level].enable = true;  in ilk_pipe_wm_get_hw_state()
3611 	struct ilk_wm_values *hw = &dev_priv->wm.hw;  in ilk_wm_get_hw_state()
6553 		if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&  in intel_init_pm()
6554 		     dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||  in intel_init_pm()
6555 		    (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&  in intel_init_pm()
6556 		     dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {  in intel_init_pm()