Lines Matching refs:rps
270 mutex_lock(&dev_priv->rps.hw_lock); in chv_set_memory_dvfs()
285 mutex_unlock(&dev_priv->rps.hw_lock); in chv_set_memory_dvfs()
292 mutex_lock(&dev_priv->rps.hw_lock); in chv_set_memory_pm5()
301 mutex_unlock(&dev_priv->rps.hw_lock); in chv_set_memory_pm5()
1812 mutex_lock(&dev_priv->rps.hw_lock); in intel_read_wm_latency()
1816 mutex_unlock(&dev_priv->rps.hw_lock); in intel_read_wm_latency()
1833 mutex_lock(&dev_priv->rps.hw_lock); in intel_read_wm_latency()
1837 mutex_unlock(&dev_priv->rps.hw_lock); in intel_read_wm_latency()
3836 limits = (dev_priv->rps.max_freq_softlimit) << 23; in intel_rps_limits()
3837 if (val <= dev_priv->rps.min_freq_softlimit) in intel_rps_limits()
3838 limits |= (dev_priv->rps.min_freq_softlimit) << 14; in intel_rps_limits()
3840 limits = dev_priv->rps.max_freq_softlimit << 24; in intel_rps_limits()
3841 if (val <= dev_priv->rps.min_freq_softlimit) in intel_rps_limits()
3842 limits |= dev_priv->rps.min_freq_softlimit << 16; in intel_rps_limits()
3854 new_power = dev_priv->rps.power; in gen6_set_rps_thresholds()
3855 switch (dev_priv->rps.power) { in gen6_set_rps_thresholds()
3857 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) in gen6_set_rps_thresholds()
3862 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) in gen6_set_rps_thresholds()
3864 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) in gen6_set_rps_thresholds()
3869 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) in gen6_set_rps_thresholds()
3874 if (val <= dev_priv->rps.min_freq_softlimit) in gen6_set_rps_thresholds()
3876 if (val >= dev_priv->rps.max_freq_softlimit) in gen6_set_rps_thresholds()
3878 if (new_power == dev_priv->rps.power) in gen6_set_rps_thresholds()
3932 dev_priv->rps.power = new_power; in gen6_set_rps_thresholds()
3933 dev_priv->rps.last_adj = 0; in gen6_set_rps_thresholds()
3940 if (val > dev_priv->rps.min_freq_softlimit) in gen6_rps_pm_mask()
3942 if (val < dev_priv->rps.max_freq_softlimit) in gen6_rps_pm_mask()
3957 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in gen6_set_rps()
3958 WARN_ON(val > dev_priv->rps.max_freq); in gen6_set_rps()
3959 WARN_ON(val < dev_priv->rps.min_freq); in gen6_set_rps()
3964 if (val != dev_priv->rps.cur_freq) { in gen6_set_rps()
3988 dev_priv->rps.cur_freq = val; in gen6_set_rps()
3996 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in valleyview_set_rps()
3997 WARN_ON(val > dev_priv->rps.max_freq); in valleyview_set_rps()
3998 WARN_ON(val < dev_priv->rps.min_freq); in valleyview_set_rps()
4004 if (val != dev_priv->rps.cur_freq) in valleyview_set_rps()
4009 dev_priv->rps.cur_freq = val; in valleyview_set_rps()
4025 u32 val = dev_priv->rps.idle_freq; in vlv_set_rps_idle()
4037 if (dev_priv->rps.cur_freq <= val) in vlv_set_rps_idle()
4046 dev_priv->rps.cur_freq = val; in vlv_set_rps_idle()
4061 mutex_lock(&dev_priv->rps.hw_lock); in gen6_rps_busy()
4062 if (dev_priv->rps.enabled) { in gen6_rps_busy()
4066 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); in gen6_rps_busy()
4068 mutex_unlock(&dev_priv->rps.hw_lock); in gen6_rps_busy()
4075 mutex_lock(&dev_priv->rps.hw_lock); in gen6_rps_idle()
4076 if (dev_priv->rps.enabled) { in gen6_rps_idle()
4080 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); in gen6_rps_idle()
4081 dev_priv->rps.last_adj = 0; in gen6_rps_idle()
4084 mutex_unlock(&dev_priv->rps.hw_lock); in gen6_rps_idle()
4091 mutex_lock(&dev_priv->rps.hw_lock); in gen6_rps_boost()
4092 val = dev_priv->rps.max_freq_softlimit; in gen6_rps_boost()
4093 if (dev_priv->rps.enabled && in gen6_rps_boost()
4095 dev_priv->rps.cur_freq < val) { in gen6_rps_boost()
4097 dev_priv->rps.last_adj = 0; in gen6_rps_boost()
4099 mutex_unlock(&dev_priv->rps.hw_lock); in gen6_rps_boost()
4216 dev_priv->rps.cur_freq = 0; in gen6_init_rps_frequencies()
4218 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; in gen6_init_rps_frequencies()
4219 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; in gen6_init_rps_frequencies()
4220 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; in gen6_init_rps_frequencies()
4224 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
4225 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
4226 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
4229 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; in gen6_init_rps_frequencies()
4231 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; in gen6_init_rps_frequencies()
4237 dev_priv->rps.efficient_freq = in gen6_init_rps_frequencies()
4240 dev_priv->rps.min_freq, in gen6_init_rps_frequencies()
4241 dev_priv->rps.max_freq); in gen6_init_rps_frequencies()
4244 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; in gen6_init_rps_frequencies()
4247 if (dev_priv->rps.max_freq_softlimit == 0) in gen6_init_rps_frequencies()
4248 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; in gen6_init_rps_frequencies()
4250 if (dev_priv->rps.min_freq_softlimit == 0) { in gen6_init_rps_frequencies()
4252 dev_priv->rps.min_freq_softlimit = in gen6_init_rps_frequencies()
4254 max(dev_priv->rps.efficient_freq, (u8) 9); in gen6_init_rps_frequencies()
4256 dev_priv->rps.min_freq_softlimit = in gen6_init_rps_frequencies()
4257 dev_priv->rps.min_freq; in gen6_init_rps_frequencies()
4272 GEN9_FREQUENCY(dev_priv->rps.rp1_freq)); in gen9_enable_rps()
4283 dev_priv->rps.power = HIGH_POWER; /* force a reset */ in gen9_enable_rps()
4284 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); in gen9_enable_rps()
4382 HSW_FREQUENCY(dev_priv->rps.rp1_freq)); in gen8_enable_rps()
4384 HSW_FREQUENCY(dev_priv->rps.rp1_freq)); in gen8_enable_rps()
4390 dev_priv->rps.max_freq_softlimit << 24 | in gen8_enable_rps()
4391 dev_priv->rps.min_freq_softlimit << 16); in gen8_enable_rps()
4411 dev_priv->rps.power = HIGH_POWER; /* force a reset */ in gen8_enable_rps()
4412 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); in gen8_enable_rps()
4426 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in gen6_enable_rps()
4500 (dev_priv->rps.max_freq_softlimit & 0xff) * 50, in gen6_enable_rps()
4502 dev_priv->rps.max_freq = pcu_mbox & 0xff; in gen6_enable_rps()
4505 dev_priv->rps.power = HIGH_POWER; /* force a reset */ in gen6_enable_rps()
4506 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); in gen6_enable_rps()
4534 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in __gen6_update_ring_freq()
4560 for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq; in __gen6_update_ring_freq()
4562 int diff = dev_priv->rps.max_freq - gpu_freq; in __gen6_update_ring_freq()
4602 mutex_lock(&dev_priv->rps.hw_lock); in gen6_update_ring_freq()
4604 mutex_unlock(&dev_priv->rps.hw_lock); in gen6_update_ring_freq()
4833 mutex_lock(&dev_priv->rps.hw_lock); in valleyview_init_gt_powersave()
4850 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); in valleyview_init_gt_powersave()
4851 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; in valleyview_init_gt_powersave()
4853 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), in valleyview_init_gt_powersave()
4854 dev_priv->rps.max_freq); in valleyview_init_gt_powersave()
4856 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); in valleyview_init_gt_powersave()
4858 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), in valleyview_init_gt_powersave()
4859 dev_priv->rps.efficient_freq); in valleyview_init_gt_powersave()
4861 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); in valleyview_init_gt_powersave()
4863 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), in valleyview_init_gt_powersave()
4864 dev_priv->rps.rp1_freq); in valleyview_init_gt_powersave()
4866 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); in valleyview_init_gt_powersave()
4868 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), in valleyview_init_gt_powersave()
4869 dev_priv->rps.min_freq); in valleyview_init_gt_powersave()
4871 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; in valleyview_init_gt_powersave()
4874 if (dev_priv->rps.max_freq_softlimit == 0) in valleyview_init_gt_powersave()
4875 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; in valleyview_init_gt_powersave()
4877 if (dev_priv->rps.min_freq_softlimit == 0) in valleyview_init_gt_powersave()
4878 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; in valleyview_init_gt_powersave()
4880 mutex_unlock(&dev_priv->rps.hw_lock); in valleyview_init_gt_powersave()
4890 mutex_lock(&dev_priv->rps.hw_lock); in cherryview_init_gt_powersave()
4899 dev_priv->rps.cz_freq = 200; in cherryview_init_gt_powersave()
4903 dev_priv->rps.cz_freq = 267; in cherryview_init_gt_powersave()
4907 dev_priv->rps.cz_freq = 333; in cherryview_init_gt_powersave()
4911 dev_priv->rps.cz_freq = 320; in cherryview_init_gt_powersave()
4915 dev_priv->rps.cz_freq = 400; in cherryview_init_gt_powersave()
4921 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); in cherryview_init_gt_powersave()
4922 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; in cherryview_init_gt_powersave()
4924 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), in cherryview_init_gt_powersave()
4925 dev_priv->rps.max_freq); in cherryview_init_gt_powersave()
4927 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); in cherryview_init_gt_powersave()
4929 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), in cherryview_init_gt_powersave()
4930 dev_priv->rps.efficient_freq); in cherryview_init_gt_powersave()
4932 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); in cherryview_init_gt_powersave()
4934 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), in cherryview_init_gt_powersave()
4935 dev_priv->rps.rp1_freq); in cherryview_init_gt_powersave()
4937 dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv); in cherryview_init_gt_powersave()
4939 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), in cherryview_init_gt_powersave()
4940 dev_priv->rps.min_freq); in cherryview_init_gt_powersave()
4942 WARN_ONCE((dev_priv->rps.max_freq | in cherryview_init_gt_powersave()
4943 dev_priv->rps.efficient_freq | in cherryview_init_gt_powersave()
4944 dev_priv->rps.rp1_freq | in cherryview_init_gt_powersave()
4945 dev_priv->rps.min_freq) & 1, in cherryview_init_gt_powersave()
4948 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; in cherryview_init_gt_powersave()
4951 if (dev_priv->rps.max_freq_softlimit == 0) in cherryview_init_gt_powersave()
4952 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; in cherryview_init_gt_powersave()
4954 if (dev_priv->rps.min_freq_softlimit == 0) in cherryview_init_gt_powersave()
4955 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; in cherryview_init_gt_powersave()
4957 mutex_unlock(&dev_priv->rps.hw_lock); in cherryview_init_gt_powersave()
4972 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in cherryview_enable_rps()
5043 dev_priv->rps.cur_freq = (val >> 8) & 0xff; in cherryview_enable_rps()
5045 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), in cherryview_enable_rps()
5046 dev_priv->rps.cur_freq); in cherryview_enable_rps()
5049 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), in cherryview_enable_rps()
5050 dev_priv->rps.efficient_freq); in cherryview_enable_rps()
5052 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); in cherryview_enable_rps()
5064 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in valleyview_enable_rps()
5127 dev_priv->rps.cur_freq = (val >> 8) & 0xff; in valleyview_enable_rps()
5129 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), in valleyview_enable_rps()
5130 dev_priv->rps.cur_freq); in valleyview_enable_rps()
5133 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), in valleyview_enable_rps()
5134 dev_priv->rps.efficient_freq); in valleyview_enable_rps()
5136 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); in valleyview_enable_rps()
5333 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4)); in __i915_gfx_val()
5651 flush_delayed_work(&dev_priv->rps.delayed_resume_work); in gen6_suspend_rps()
5686 mutex_lock(&dev_priv->rps.hw_lock); in intel_disable_gt_powersave()
5696 dev_priv->rps.enabled = false; in intel_disable_gt_powersave()
5697 mutex_unlock(&dev_priv->rps.hw_lock); in intel_disable_gt_powersave()
5705 rps.delayed_resume_work.work); in intel_gen6_powersave_work()
5708 mutex_lock(&dev_priv->rps.hw_lock); in intel_gen6_powersave_work()
5728 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq); in intel_gen6_powersave_work()
5729 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq); in intel_gen6_powersave_work()
5731 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq); in intel_gen6_powersave_work()
5732 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq); in intel_gen6_powersave_work()
5734 dev_priv->rps.enabled = true; in intel_gen6_powersave_work()
5738 mutex_unlock(&dev_priv->rps.hw_lock); in intel_gen6_powersave_work()
5769 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, in intel_enable_gt_powersave()
5783 dev_priv->rps.enabled = false; in intel_reset_gt_powersave()
6633 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in sandybridge_pcode_read()
6658 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); in sandybridge_pcode_write()
6720 int div, czclk_freq = dev_priv->rps.cz_freq; in chv_gpu_freq()
6731 int mul, czclk_freq = dev_priv->rps.cz_freq; in chv_freq_opcode()
6769 mutex_init(&dev_priv->rps.hw_lock); in intel_pm_setup()
6771 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, in intel_pm_setup()