359 			      enum pipe pipe, int plane)  in vlv_get_fifo_size()  argument
364 	switch (pipe) {  in vlv_get_fifo_size()
403 		      pipe_name(pipe), plane == 0 ? "primary" : "sprite",  in vlv_get_fifo_size()
404 		      plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),  in vlv_get_fifo_size()
848 	enum pipe pipe = crtc->pipe;  in vlv_write_wm_values()  local
850 	I915_WRITE(VLV_DDL(pipe),  in vlv_write_wm_values()
851 		   (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |  in vlv_write_wm_values()
852 		   (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |  in vlv_write_wm_values()
853 		   (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |  in vlv_write_wm_values()
854 		   (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));  in vlv_write_wm_values()
858 		   FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |  in vlv_write_wm_values()
859 		   FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |  in vlv_write_wm_values()
860 		   FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));  in vlv_write_wm_values()
862 		   FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |  in vlv_write_wm_values()
863 		   FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |  in vlv_write_wm_values()
864 		   FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));  in vlv_write_wm_values()
870 			   FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |  in vlv_write_wm_values()
871 			   FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));  in vlv_write_wm_values()
873 			   FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |  in vlv_write_wm_values()
874 			   FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));  in vlv_write_wm_values()
876 			   FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |  in vlv_write_wm_values()
877 			   FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));  in vlv_write_wm_values()
880 			   FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |  in vlv_write_wm_values()
881 			   FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |  in vlv_write_wm_values()
882 			   FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |  in vlv_write_wm_values()
883 			   FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |  in vlv_write_wm_values()
884 			   FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |  in vlv_write_wm_values()
885 			   FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |  in vlv_write_wm_values()
886 			   FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |  in vlv_write_wm_values()
887 			   FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |  in vlv_write_wm_values()
888 			   FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));  in vlv_write_wm_values()
891 			   FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |  in vlv_write_wm_values()
892 			   FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));  in vlv_write_wm_values()
895 			   FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |  in vlv_write_wm_values()
896 			   FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |  in vlv_write_wm_values()
897 			   FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |  in vlv_write_wm_values()
898 			   FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |  in vlv_write_wm_values()
899 			   FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |  in vlv_write_wm_values()
900 			   FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));  in vlv_write_wm_values()
986 	enum pipe pipe = INVALID_PIPE;  in vlv_compute_sr_wm()  local
995 	if (crtc && to_intel_crtc(crtc)->pipe != PIPE_C) {  in vlv_compute_sr_wm()
996 		pipe = to_intel_crtc(crtc)->pipe;  in vlv_compute_sr_wm()
997 		num_planes = !!wm->pipe[pipe].primary +  in vlv_compute_sr_wm()
998 			!!wm->pipe[pipe].sprite[0] +  in vlv_compute_sr_wm()
999 			!!wm->pipe[pipe].sprite[1];  in vlv_compute_sr_wm()
1013 		if (plane->pipe != pipe)  in vlv_compute_sr_wm()
1030 	enum pipe pipe = intel_crtc->pipe;  in valleyview_update_wm()  local
1034 	wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);  in valleyview_update_wm()
1035 	wm.pipe[pipe].primary = vlv_compute_wm(intel_crtc,  in valleyview_update_wm()
1037 					       vlv_get_fifo_size(dev, pipe, 0));  in valleyview_update_wm()
1039 	wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);  in valleyview_update_wm()
1040 	wm.pipe[pipe].cursor = vlv_compute_wm(intel_crtc,  in valleyview_update_wm()
1050 		      "SR: plane=%d, cursor=%d\n", pipe_name(pipe),  in valleyview_update_wm()
1051 		      wm.pipe[pipe].primary, wm.pipe[pipe].cursor,  in valleyview_update_wm()
1084 	enum pipe pipe = intel_crtc->pipe;  in valleyview_update_sprite_wm()  local
1090 		wm.ddl[pipe].sprite[sprite] =  in valleyview_update_sprite_wm()
1093 		wm.pipe[pipe].sprite[sprite] =  in valleyview_update_sprite_wm()
1096 				       vlv_get_fifo_size(dev, pipe, sprite+1));  in valleyview_update_sprite_wm()
1098 		wm.ddl[pipe].sprite[sprite] = 0;  in valleyview_update_sprite_wm()
1099 		wm.pipe[pipe].sprite[sprite] = 0;  in valleyview_update_sprite_wm()
1108 		      "SR: plane=%d, cursor=%d\n", pipe_name(pipe),  in valleyview_update_sprite_wm()
1109 		      sprite_name(pipe, sprite),  in valleyview_update_sprite_wm()
1110 		      wm.pipe[pipe].sprite[sprite],  in valleyview_update_sprite_wm()
2038 	enum pipe pipe = intel_crtc->pipe;  in ilk_compute_wm_parameters()  local
2068 		if (intel_plane->pipe == pipe) {  in ilk_compute_wm_parameters()
2312 		enum pipe pipe = intel_crtc->pipe;  in ilk_compute_wm_results()  local
2319 		results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;  in ilk_compute_wm_results()
2321 		results->wm_pipe[pipe] =  in ilk_compute_wm_results()
2357 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))  argument
2358 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))  argument
2369 	enum pipe pipe;  in ilk_compute_wm_dirty()  local
2372 	for_each_pipe(dev_priv, pipe) {  in ilk_compute_wm_dirty()
2373 		if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {  in ilk_compute_wm_dirty()
2374 			dirty |= WM_DIRTY_LINETIME(pipe);  in ilk_compute_wm_dirty()
2379 		if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {  in ilk_compute_wm_dirty()
2380 			dirty |= WM_DIRTY_PIPE(pipe);  in ilk_compute_wm_dirty()
2596 	enum pipe pipe;  in skl_ddb_get_hw_state()  local
2600 	for_each_pipe(dev_priv, pipe) {  in skl_ddb_get_hw_state()
2601 		for_each_plane(dev_priv, pipe, plane) {  in skl_ddb_get_hw_state()
2602 			val = I915_READ(PLANE_BUF_CFG(pipe, plane));  in skl_ddb_get_hw_state()
2603 			skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],  in skl_ddb_get_hw_state()
2607 		val = I915_READ(CUR_BUF_CFG(pipe));  in skl_ddb_get_hw_state()
2608 		skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);  in skl_ddb_get_hw_state()
2652 	enum pipe pipe = intel_crtc->pipe;  in skl_allocate_pipe_ddb()  local
2653 	struct skl_ddb_entry *alloc = &ddb->pipe[pipe];  in skl_allocate_pipe_ddb()
2662 		memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));  in skl_allocate_pipe_ddb()
2663 		memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));  in skl_allocate_pipe_ddb()
2668 	ddb->cursor[pipe].start = alloc->end - cursor_blocks;  in skl_allocate_pipe_ddb()
2669 	ddb->cursor[pipe].end = alloc->end;  in skl_allocate_pipe_ddb()
2675 	for_each_plane(dev_priv, pipe, plane) {  in skl_allocate_pipe_ddb()
2714 		ddb->plane[pipe][plane].start = start;  in skl_allocate_pipe_ddb()
2715 		ddb->plane[pipe][plane].end = start + plane_blocks;  in skl_allocate_pipe_ddb()
2783 	enum pipe pipe = intel_crtc->pipe;  in skl_ddb_allocation_changed()  local
2785 	if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],  in skl_ddb_allocation_changed()
2786 		   sizeof(new_ddb->plane[pipe])))  in skl_ddb_allocation_changed()
2789 	if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],  in skl_ddb_allocation_changed()
2790 		    sizeof(new_ddb->cursor[pipe])))  in skl_ddb_allocation_changed()
2819 	enum pipe pipe = intel_crtc->pipe;  in skl_compute_wm_pipe_parameters()  local
2860 		if (intel_plane->pipe == pipe &&  in skl_compute_wm_pipe_parameters()
2945 				 enum pipe pipe,  in skl_compute_wm_level()  argument
2954 		ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);  in skl_compute_wm_level()
2964 	ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);  in skl_compute_wm_level()
3008 		skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,  in skl_compute_pipe_wm()
3024 	enum pipe pipe = intel_crtc->pipe;  in skl_compute_wm_results()  local
3038 			r->plane[pipe][i][level] = temp;  in skl_compute_wm_results()
3049 		r->cursor[pipe][level] = temp;  in skl_compute_wm_results()
3061 		r->plane_trans[pipe][i] = temp;  in skl_compute_wm_results()
3070 	r->cursor_trans[pipe] = temp;  in skl_compute_wm_results()
3072 	r->wm_linetime[pipe] = p_wm->linetime;  in skl_compute_wm_results()
3092 		enum pipe pipe = crtc->pipe;  in skl_write_wm_values()  local
3094 		if (!new->dirty[pipe])  in skl_write_wm_values()
3097 		I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);  in skl_write_wm_values()
3101 				I915_WRITE(PLANE_WM(pipe, i, level),  in skl_write_wm_values()
3102 					   new->plane[pipe][i][level]);  in skl_write_wm_values()
3103 			I915_WRITE(CUR_WM(pipe, level),  in skl_write_wm_values()
3104 				   new->cursor[pipe][level]);  in skl_write_wm_values()
3107 			I915_WRITE(PLANE_WM_TRANS(pipe, i),  in skl_write_wm_values()
3108 				   new->plane_trans[pipe][i]);  in skl_write_wm_values()
3109 		I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);  in skl_write_wm_values()
3113 					    PLANE_BUF_CFG(pipe, i),  in skl_write_wm_values()
3114 					    &new->ddb.plane[pipe][i]);  in skl_write_wm_values()
3116 		skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),  in skl_write_wm_values()
3117 				    &new->ddb.cursor[pipe]);  in skl_write_wm_values()
3146 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)  in skl_wm_flush_pipe()  argument
3150 	DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);  in skl_wm_flush_pipe()
3152 	for_each_plane(dev_priv, pipe, plane) {  in skl_wm_flush_pipe()
3153 		I915_WRITE(PLANE_SURF(pipe, plane),  in skl_wm_flush_pipe()
3154 			   I915_READ(PLANE_SURF(pipe, plane)));  in skl_wm_flush_pipe()
3156 	I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));  in skl_wm_flush_pipe()
3162 			    enum pipe pipe)  in skl_ddb_allocation_included()  argument
3166 	old_size = skl_ddb_entry_size(&old->pipe[pipe]);  in skl_ddb_allocation_included()
3167 	new_size = skl_ddb_entry_size(&new->pipe[pipe]);  in skl_ddb_allocation_included()
3170 	       new->pipe[pipe].start >= old->pipe[pipe].start &&  in skl_ddb_allocation_included()
3171 	       new->pipe[pipe].end <= old->pipe[pipe].end;  in skl_ddb_allocation_included()
3181 	enum pipe pipe;  in skl_flush_wm_values()  local
3197 		pipe = crtc->pipe;  in skl_flush_wm_values()
3199 		if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))  in skl_flush_wm_values()
3202 		skl_wm_flush_pipe(dev_priv, pipe, 1);  in skl_flush_wm_values()
3203 		intel_wait_for_vblank(dev, pipe);  in skl_flush_wm_values()
3205 		reallocated[pipe] = true;  in skl_flush_wm_values()
3220 		pipe = crtc->pipe;  in skl_flush_wm_values()
3222 		if (reallocated[pipe])  in skl_flush_wm_values()
3225 		if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <  in skl_flush_wm_values()
3226 		    skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {  in skl_flush_wm_values()
3227 			skl_wm_flush_pipe(dev_priv, pipe, 2);  in skl_flush_wm_values()
3228 			intel_wait_for_vblank(dev, pipe);  in skl_flush_wm_values()
3229 			reallocated[pipe] = true;  in skl_flush_wm_values()
3243 		pipe = crtc->pipe;  in skl_flush_wm_values()
3249 		if (reallocated[pipe])  in skl_flush_wm_values()
3252 		skl_wm_flush_pipe(dev_priv, pipe, 3);  in skl_flush_wm_values()
3302 		if (this_crtc->pipe == intel_crtc->pipe)  in skl_update_other_pipe_wm()
3320 		r->dirty[intel_crtc->pipe] = true;  in skl_update_other_pipe_wm()
3343 	results->dirty[intel_crtc->pipe] = true;  in skl_update_wm()
3447 		intel_wait_for_vblank(dev, intel_plane->pipe);  in ilk_update_sprite_wm()
3503 	enum pipe pipe = intel_crtc->pipe;  in skl_pipe_wm_get_hw_state()  local
3509 	hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));  in skl_pipe_wm_get_hw_state()
3513 			hw->plane[pipe][i][level] =  in skl_pipe_wm_get_hw_state()
3514 					I915_READ(PLANE_WM(pipe, i, level));  in skl_pipe_wm_get_hw_state()
3515 		hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));  in skl_pipe_wm_get_hw_state()
3519 		hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));  in skl_pipe_wm_get_hw_state()
3520 	hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));  in skl_pipe_wm_get_hw_state()
3525 	hw->dirty[pipe] = true;  in skl_pipe_wm_get_hw_state()
3527 	active->linetime = hw->wm_linetime[pipe];  in skl_pipe_wm_get_hw_state()
3531 			temp = hw->plane[pipe][i][level];  in skl_pipe_wm_get_hw_state()
3535 		temp = hw->cursor[pipe][level];  in skl_pipe_wm_get_hw_state()
3540 		temp = hw->plane_trans[pipe][i];  in skl_pipe_wm_get_hw_state()
3544 	temp = hw->cursor_trans[pipe];  in skl_pipe_wm_get_hw_state()
3566 	enum pipe pipe = intel_crtc->pipe;  in ilk_pipe_wm_get_hw_state()  local
3573 	hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);  in ilk_pipe_wm_get_hw_state()
3575 		hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));  in ilk_pipe_wm_get_hw_state()
3582 		u32 tmp = hw->wm_pipe[pipe];  in ilk_pipe_wm_get_hw_state()
3594 		active->linetime = hw->wm_linetime[pipe];  in ilk_pipe_wm_get_hw_state()
5801 	int pipe;  in g4x_disable_trickle_feed()  local
5803 	for_each_pipe(dev_priv, pipe) {  in g4x_disable_trickle_feed()
5804 		I915_WRITE(DSPCNTR(pipe),  in g4x_disable_trickle_feed()
5805 			   I915_READ(DSPCNTR(pipe)) |  in g4x_disable_trickle_feed()
5807 		intel_flush_primary_plane(dev_priv, pipe);  in g4x_disable_trickle_feed()
5902 	int pipe;  in cpt_init_clock_gating()  local
5918 	for_each_pipe(dev_priv, pipe) {  in cpt_init_clock_gating()
5919 		val = I915_READ(TRANS_CHICKEN2(pipe));  in cpt_init_clock_gating()
5927 		I915_WRITE(TRANS_CHICKEN2(pipe), val);  in cpt_init_clock_gating()
5930 	for_each_pipe(dev_priv, pipe) {  in cpt_init_clock_gating()
5931 		I915_WRITE(TRANS_CHICKEN1(pipe),  in cpt_init_clock_gating()
6096 	enum pipe pipe;  in broadwell_init_clock_gating()  local
6110 	for_each_pipe(dev_priv, pipe) {  in broadwell_init_clock_gating()
6111 		I915_WRITE(CHICKEN_PIPESL_1(pipe),  in broadwell_init_clock_gating()
6112 			   I915_READ(CHICKEN_PIPESL_1(pipe)) |  in broadwell_init_clock_gating()