121 		dev_priv->mem_freq = 533;  in i915_pineview_get_mem_freq()
124 		dev_priv->mem_freq = 667;  in i915_pineview_get_mem_freq()
127 		dev_priv->mem_freq = 800;  in i915_pineview_get_mem_freq()
146 		dev_priv->mem_freq = 800;  in i915_ironlake_get_mem_freq()
149 		dev_priv->mem_freq = 1066;  in i915_ironlake_get_mem_freq()
152 		dev_priv->mem_freq = 1333;  in i915_ironlake_get_mem_freq()
155 		dev_priv->mem_freq = 1600;  in i915_ironlake_get_mem_freq()
160 		dev_priv->mem_freq = 0;  in i915_ironlake_get_mem_freq()
164 	dev_priv->ips.r_t = dev_priv->mem_freq;  in i915_ironlake_get_mem_freq()
257 		    fsb == latency->fsb_freq && mem == latency->mem_freq)  in intel_get_cxsr_latency()
645 					 dev_priv->fsb_freq, dev_priv->mem_freq);  in pineview_update_wm()
4839 		dev_priv->mem_freq = 800;  in valleyview_init_gt_powersave()
4842 		dev_priv->mem_freq = 1066;  in valleyview_init_gt_powersave()
4845 		dev_priv->mem_freq = 1333;  in valleyview_init_gt_powersave()
4848 	DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);  in valleyview_init_gt_powersave()
4900 		dev_priv->mem_freq = 1600;  in cherryview_init_gt_powersave()
4904 		dev_priv->mem_freq = 1600;  in cherryview_init_gt_powersave()
4908 		dev_priv->mem_freq = 2000;  in cherryview_init_gt_powersave()
4912 		dev_priv->mem_freq = 1600;  in cherryview_init_gt_powersave()
4916 		dev_priv->mem_freq = 1600;  in cherryview_init_gt_powersave()
4919 	DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);  in cherryview_init_gt_powersave()
6588 					    dev_priv->mem_freq)) {  in intel_init_pm()
6593 				 dev_priv->fsb_freq, dev_priv->mem_freq);  in intel_init_pm()
6698 	int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);  in byt_gpu_freq()
6709 	int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);  in byt_freq_opcode()