1605 					 int level, bool is_sprite)  in ilk_plane_wm_reg_max()  argument
1609 		return level == 0 ? 255 : 2047;  in ilk_plane_wm_reg_max()
1612 		return level == 0 ? 127 : 1023;  in ilk_plane_wm_reg_max()
1615 		return level == 0 ? 127 : 511;  in ilk_plane_wm_reg_max()
1618 		return level == 0 ? 63 : 255;  in ilk_plane_wm_reg_max()
1622 					  int level)  in ilk_cursor_wm_reg_max()  argument
1625 		return level == 0 ? 63 : 255;  in ilk_cursor_wm_reg_max()
1627 		return level == 0 ? 31 : 63;  in ilk_cursor_wm_reg_max()
1640 				     int level,  in ilk_plane_wm_max()  argument
1652 	if (level == 0 || config->num_pipes_active > 1) {  in ilk_plane_wm_max()
1666 		if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {  in ilk_plane_wm_max()
1676 	return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));  in ilk_plane_wm_max()
1681 				      int level,  in ilk_cursor_wm_max()  argument
1685 	if (level > 0 && config->num_pipes_active > 1)  in ilk_cursor_wm_max()
1689 	return ilk_cursor_wm_reg_max(dev, level);  in ilk_cursor_wm_max()
1693 				    int level,  in ilk_compute_wm_maximums()  argument
1698 	max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);  in ilk_compute_wm_maximums()
1699 	max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);  in ilk_compute_wm_maximums()
1700 	max->cur = ilk_cursor_wm_max(dev, level, config);  in ilk_compute_wm_maximums()
1705 					int level,  in ilk_compute_wm_reg_maximums()  argument
1708 	max->pri = ilk_plane_wm_reg_max(dev, level, false);  in ilk_compute_wm_reg_maximums()
1709 	max->spr = ilk_plane_wm_reg_max(dev, level, true);  in ilk_compute_wm_reg_maximums()
1710 	max->cur = ilk_cursor_wm_reg_max(dev, level);  in ilk_compute_wm_reg_maximums()
1714 static bool ilk_validate_wm_level(int level,  in ilk_validate_wm_level()  argument
1735 	if (level == 0 && !result->enable) {  in ilk_validate_wm_level()
1738 				      level, result->pri_val, max->pri);  in ilk_validate_wm_level()
1741 				      level, result->spr_val, max->spr);  in ilk_validate_wm_level()
1744 				      level, result->cur_val, max->cur);  in ilk_validate_wm_level()
1756 				 int level,  in ilk_compute_wm_level()  argument
1760 	uint16_t pri_latency = dev_priv->wm.pri_latency[level];  in ilk_compute_wm_level()
1761 	uint16_t spr_latency = dev_priv->wm.spr_latency[level];  in ilk_compute_wm_level()
1762 	uint16_t cur_latency = dev_priv->wm.cur_latency[level];  in ilk_compute_wm_level()
1765 	if (level > 0) {  in ilk_compute_wm_level()
1771 	result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);  in ilk_compute_wm_level()
1808 		int level, max_level = ilk_wm_max_level(dev);  in intel_read_wm_latency()  local
1869 		for (level = 1; level <= max_level; level++)  in intel_read_wm_latency()
1870 			if (wm[level] != 0)  in intel_read_wm_latency()
1871 				wm[level] += 2;  in intel_read_wm_latency()
1873 				for (i = level + 1; i <= max_level; i++)  in intel_read_wm_latency()
1940 	int level, max_level = ilk_wm_max_level(dev);  in intel_print_wm_latency()  local
1942 	for (level = 0; level <= max_level; level++) {  in intel_print_wm_latency()
1943 		unsigned int latency = wm[level];  in intel_print_wm_latency()
1947 				  name, level);  in intel_print_wm_latency()
1957 		else if (level > 0)  in intel_print_wm_latency()
1961 			      name, level, wm[level],  in intel_print_wm_latency()
1969 	int level, max_level = ilk_wm_max_level(dev_priv->dev);  in ilk_increase_wm_latency()  local
1975 	for (level = 1; level <= max_level; level++)  in ilk_increase_wm_latency()
1976 		wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));  in ilk_increase_wm_latency()
2100 	int level, max_level = ilk_wm_max_level(dev);  in intel_compute_pipe_wm()  local
2135 	for (level = 1; level <= max_level; level++) {  in intel_compute_pipe_wm()
2138 		ilk_compute_wm_level(dev_priv, level, params, &wm);  in intel_compute_pipe_wm()
2145 		if (!ilk_validate_wm_level(level, &max, &wm))  in intel_compute_pipe_wm()
2148 		pipe_wm->wm[level] = wm;  in intel_compute_pipe_wm()
2158 			       int level,  in ilk_merge_wm_level()  argument
2167 		const struct intel_wm_level *wm = &active->wm[level];  in ilk_merge_wm_level()
2195 	int level, max_level = ilk_wm_max_level(dev);  in ilk_wm_merge()  local
2207 	for (level = 1; level <= max_level; level++) {  in ilk_wm_merge()
2208 		struct intel_wm_level *wm = &merged->wm[level];  in ilk_wm_merge()
2210 		ilk_merge_wm_level(dev, level, wm);  in ilk_wm_merge()
2212 		if (level > last_enabled_level)  in ilk_wm_merge()
2214 		else if (!ilk_validate_wm_level(level, max, wm))  in ilk_wm_merge()
2216 			last_enabled_level = level - 1;  in ilk_wm_merge()
2236 		for (level = 2; level <= max_level; level++) {  in ilk_wm_merge()
2237 			struct intel_wm_level *wm = &merged->wm[level];  in ilk_wm_merge()
2251 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)  in ilk_wm_lp_latency()  argument
2256 		return 2 * level;  in ilk_wm_lp_latency()
2258 		return dev_priv->wm.pri_latency[level];  in ilk_wm_lp_latency()
2267 	int level, wm_lp;  in ilk_compute_wm_results()  local
2276 		level = ilk_wm_lp_to_level(wm_lp, merged);  in ilk_compute_wm_results()
2278 		r = &merged->wm[level];  in ilk_compute_wm_results()
2285 			(ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |  in ilk_compute_wm_results()
2334 	int level, max_level = ilk_wm_max_level(dev);  in ilk_find_best_result()  local
2337 	for (level = 1; level <= max_level; level++) {  in ilk_find_best_result()
2338 		if (r1->wm[level].enable)  in ilk_find_best_result()
2339 			level1 = level;  in ilk_find_best_result()
2340 		if (r2->wm[level].enable)  in ilk_find_best_result()
2341 			level2 = level;  in ilk_find_best_result()
2870 				 int level,  in skl_compute_plane_wm()  argument
2874 	uint32_t latency = dev_priv->wm.skl_latency[level];  in skl_compute_plane_wm()
2925 	if (level >= 1 && level <= 7) {  in skl_compute_plane_wm()
2946 				 int level,  in skl_compute_wm_level()  argument
2959 						level,  in skl_compute_wm_level()
2966 						 ddb_blocks, level,  in skl_compute_wm_level()
3005 	int level, max_level = ilk_wm_max_level(dev);  in skl_compute_pipe_wm()  local
3007 	for (level = 0; level <= max_level; level++) {  in skl_compute_pipe_wm()
3009 				     level, intel_num_planes(intel_crtc),  in skl_compute_pipe_wm()
3010 				     &pipe_wm->wm[level]);  in skl_compute_pipe_wm()
3023 	int level, max_level = ilk_wm_max_level(dev);  in skl_compute_wm_results()  local
3028 	for (level = 0; level <= max_level; level++) {  in skl_compute_wm_results()
3032 			temp |= p_wm->wm[level].plane_res_l[i] <<  in skl_compute_wm_results()
3034 			temp |= p_wm->wm[level].plane_res_b[i];  in skl_compute_wm_results()
3035 			if (p_wm->wm[level].plane_en[i])  in skl_compute_wm_results()
3038 			r->plane[pipe][i][level] = temp;  in skl_compute_wm_results()
3043 		temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;  in skl_compute_wm_results()
3044 		temp |= p_wm->wm[level].cursor_res_b;  in skl_compute_wm_results()
3046 		if (p_wm->wm[level].cursor_en)  in skl_compute_wm_results()
3049 		r->cursor[pipe][level] = temp;  in skl_compute_wm_results()
3091 		int i, level, max_level = ilk_wm_max_level(dev);  in skl_write_wm_values()  local
3099 		for (level = 0; level <= max_level; level++) {  in skl_write_wm_values()
3101 				I915_WRITE(PLANE_WM(pipe, i, level),  in skl_write_wm_values()
3102 					   new->plane[pipe][i][level]);  in skl_write_wm_values()
3103 			I915_WRITE(CUR_WM(pipe, level),  in skl_write_wm_values()
3104 				   new->cursor[pipe][level]);  in skl_write_wm_values()
3457 				     int level)  in skl_pipe_wm_active_state()  argument
3463 			active->wm[level].plane_en[i] = is_enabled;  in skl_pipe_wm_active_state()
3464 			active->wm[level].plane_res_b[i] =  in skl_pipe_wm_active_state()
3466 			active->wm[level].plane_res_l[i] =  in skl_pipe_wm_active_state()
3470 			active->wm[level].cursor_en = is_enabled;  in skl_pipe_wm_active_state()
3471 			active->wm[level].cursor_res_b =  in skl_pipe_wm_active_state()
3473 			active->wm[level].cursor_res_l =  in skl_pipe_wm_active_state()
3504 	int level, i, max_level;  in skl_pipe_wm_get_hw_state()  local
3511 	for (level = 0; level <= max_level; level++) {  in skl_pipe_wm_get_hw_state()
3513 			hw->plane[pipe][i][level] =  in skl_pipe_wm_get_hw_state()
3514 					I915_READ(PLANE_WM(pipe, i, level));  in skl_pipe_wm_get_hw_state()
3515 		hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));  in skl_pipe_wm_get_hw_state()
3529 	for (level = 0; level <= max_level; level++) {  in skl_pipe_wm_get_hw_state()
3531 			temp = hw->plane[pipe][i][level];  in skl_pipe_wm_get_hw_state()
3533 						false, i, level);  in skl_pipe_wm_get_hw_state()
3535 		temp = hw->cursor[pipe][level];  in skl_pipe_wm_get_hw_state()
3536 		skl_pipe_wm_active_state(temp, active, false, true, i, level);  in skl_pipe_wm_get_hw_state()
3596 		int level, max_level = ilk_wm_max_level(dev);  in ilk_pipe_wm_get_hw_state()  local
3603 		for (level = 0; level <= max_level; level++)  in ilk_pipe_wm_get_hw_state()
3604 			active->wm[level].enable = true;  in ilk_pipe_wm_get_hw_state()