164 	dev_priv->ips.r_t = dev_priv->mem_freq;  in i915_ironlake_get_mem_freq()
196 		dev_priv->ips.c_m = 0;  in i915_ironlake_get_mem_freq()
198 		dev_priv->ips.c_m = 1;  in i915_ironlake_get_mem_freq()
200 		dev_priv->ips.c_m = 2;  in i915_ironlake_get_mem_freq()
3757 	dev_priv->ips.fmax = fmax; /* IPS callback will increase this */  in ironlake_enable_drps()
3758 	dev_priv->ips.fstart = fstart;  in ironlake_enable_drps()
3760 	dev_priv->ips.max_delay = fstart;  in ironlake_enable_drps()
3761 	dev_priv->ips.min_delay = fmin;  in ironlake_enable_drps()
3762 	dev_priv->ips.cur_delay = fstart;  in ironlake_enable_drps()
3785 	dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +  in ironlake_enable_drps()
3787 	dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);  in ironlake_enable_drps()
3788 	dev_priv->ips.last_count2 = I915_READ(0x112f4);  in ironlake_enable_drps()
3789 	dev_priv->ips.last_time2 = ktime_get_raw_ns();  in ironlake_enable_drps()
3811 	ironlake_set_drps(dev, dev_priv->ips.fstart);  in ironlake_disable_drps()
5179 	diff1 = now - dev_priv->ips.last_time1;  in __i915_chipset_val()
5187 		return dev_priv->ips.chipset_power;  in __i915_chipset_val()
5196 	if (total_count < dev_priv->ips.last_count1) {  in __i915_chipset_val()
5197 		diff = ~0UL - dev_priv->ips.last_count1;  in __i915_chipset_val()
5200 		diff = total_count - dev_priv->ips.last_count1;  in __i915_chipset_val()
5204 		if (cparams[i].i == dev_priv->ips.c_m &&  in __i915_chipset_val()
5205 		    cparams[i].t == dev_priv->ips.r_t) {  in __i915_chipset_val()
5216 	dev_priv->ips.last_count1 = total_count;  in __i915_chipset_val()
5217 	dev_priv->ips.last_time1 = now;  in __i915_chipset_val()
5219 	dev_priv->ips.chipset_power = ret;  in __i915_chipset_val()
5287 	diffms = now - dev_priv->ips.last_time2;  in __i915_update_gfx_val()
5296 	if (count < dev_priv->ips.last_count2) {  in __i915_update_gfx_val()
5297 		diff = ~0UL - dev_priv->ips.last_count2;  in __i915_update_gfx_val()
5300 		diff = count - dev_priv->ips.last_count2;  in __i915_update_gfx_val()
5303 	dev_priv->ips.last_count2 = count;  in __i915_update_gfx_val()
5304 	dev_priv->ips.last_time2 = now;  in __i915_update_gfx_val()
5309 	dev_priv->ips.gfx_power = diff;  in __i915_update_gfx_val()
5353 	corr2 = (corr * dev_priv->ips.corr);  in __i915_gfx_val()
5360 	return dev_priv->ips.gfx_power + state2;  in __i915_gfx_val()
5425 	if (dev_priv->ips.max_delay > dev_priv->ips.fmax)  in i915_gpu_raise()
5426 		dev_priv->ips.max_delay--;  in i915_gpu_raise()
5453 	if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)  in i915_gpu_lower()
5454 		dev_priv->ips.max_delay++;  in i915_gpu_lower()
5508 	dev_priv->ips.max_delay = dev_priv->ips.fstart;  in i915_gpu_turbo_disable()
5510 	if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))  in i915_gpu_turbo_disable()
5626 	dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);  in intel_init_emon()