3857 		if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)  in gen6_set_rps_thresholds()
3862 		if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)  in gen6_set_rps_thresholds()
4231 	dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;  in gen6_init_rps_frequencies()
4237 			dev_priv->rps.efficient_freq =  in gen6_init_rps_frequencies()
4254 				max(dev_priv->rps.efficient_freq, (u8) 9);  in gen6_init_rps_frequencies()
4856 	dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);  in valleyview_init_gt_powersave()
4858 			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),  in valleyview_init_gt_powersave()
4859 			 dev_priv->rps.efficient_freq);  in valleyview_init_gt_powersave()
4927 	dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);  in cherryview_init_gt_powersave()
4929 			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),  in cherryview_init_gt_powersave()
4930 			 dev_priv->rps.efficient_freq);  in cherryview_init_gt_powersave()
4943 		   dev_priv->rps.efficient_freq |  in cherryview_init_gt_powersave()
5049 			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),  in cherryview_enable_rps()
5050 			 dev_priv->rps.efficient_freq);  in cherryview_enable_rps()
5052 	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);  in cherryview_enable_rps()
5133 			 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),  in valleyview_enable_rps()
5134 			 dev_priv->rps.efficient_freq);  in valleyview_enable_rps()
5136 	valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);  in valleyview_enable_rps()
5731 	WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);  in intel_gen6_powersave_work()
5732 	WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);  in intel_gen6_powersave_work()