707 			    const struct intel_watermark_params *display,  in g4x_compute_wm0()  argument
723 		*plane_wm = display->guard_size;  in g4x_compute_wm0()
735 	tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;  in g4x_compute_wm0()
738 	entries = DIV_ROUND_UP(entries, display->cacheline_size);  in g4x_compute_wm0()
739 	*plane_wm = entries + display->guard_size;  in g4x_compute_wm0()
740 	if (*plane_wm > (int)display->max_wm)  in g4x_compute_wm0()
741 		*plane_wm = display->max_wm;  in g4x_compute_wm0()
767 			   const struct intel_watermark_params *display,  in g4x_check_srwm()  argument
773 	if (display_wm > display->max_wm) {  in g4x_check_srwm()
775 			      display_wm, display->max_wm);  in g4x_check_srwm()
796 			     const struct intel_watermark_params *display,  in g4x_compute_srwm()  argument
828 	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);  in g4x_compute_srwm()
829 	*display_wm = entries + display->guard_size;  in g4x_compute_srwm()
838 			      display, cursor);  in g4x_compute_srwm()
1276 	fifo_size = dev_priv->display.get_fifo_size(dev, 0);  in i9xx_update_wm()
1298 	fifo_size = dev_priv->display.get_fifo_size(dev, 1);  in i9xx_update_wm()
1404 				       dev_priv->display.get_fifo_size(dev, 0),  in i845_update_wm()
3674 	if (dev_priv->display.update_wm)  in intel_update_watermarks()
3675 		dev_priv->display.update_wm(crtc);  in intel_update_watermarks()
3687 	if (dev_priv->display.update_sprite_wm)  in intel_update_sprite_watermarks()
3688 		dev_priv->display.update_sprite_wm(plane, crtc,  in intel_update_sprite_watermarks()
6520 	if (dev_priv->display.init_clock_gating)  in intel_init_clock_gating()
6521 		dev_priv->display.init_clock_gating(dev);  in intel_init_clock_gating()
6547 		dev_priv->display.init_clock_gating = skl_init_clock_gating;  in intel_init_pm()
6548 		dev_priv->display.update_wm = skl_update_wm;  in intel_init_pm()
6549 		dev_priv->display.update_sprite_wm = skl_update_sprite_wm;  in intel_init_pm()
6557 			dev_priv->display.update_wm = ilk_update_wm;  in intel_init_pm()
6558 			dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;  in intel_init_pm()
6565 			dev_priv->display.init_clock_gating = ironlake_init_clock_gating;  in intel_init_pm()
6567 			dev_priv->display.init_clock_gating = gen6_init_clock_gating;  in intel_init_pm()
6569 			dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;  in intel_init_pm()
6571 			dev_priv->display.init_clock_gating = haswell_init_clock_gating;  in intel_init_pm()
6573 			dev_priv->display.init_clock_gating = broadwell_init_clock_gating;  in intel_init_pm()
6575 		dev_priv->display.update_wm = valleyview_update_wm;  in intel_init_pm()
6576 		dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;  in intel_init_pm()
6577 		dev_priv->display.init_clock_gating =  in intel_init_pm()
6580 		dev_priv->display.update_wm = valleyview_update_wm;  in intel_init_pm()
6581 		dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;  in intel_init_pm()
6582 		dev_priv->display.init_clock_gating =  in intel_init_pm()
6596 			dev_priv->display.update_wm = NULL;  in intel_init_pm()
6598 			dev_priv->display.update_wm = pineview_update_wm;  in intel_init_pm()
6599 		dev_priv->display.init_clock_gating = gen3_init_clock_gating;  in intel_init_pm()
6601 		dev_priv->display.update_wm = g4x_update_wm;  in intel_init_pm()
6602 		dev_priv->display.init_clock_gating = g4x_init_clock_gating;  in intel_init_pm()
6604 		dev_priv->display.update_wm = i965_update_wm;  in intel_init_pm()
6606 			dev_priv->display.init_clock_gating = crestline_init_clock_gating;  in intel_init_pm()
6608 			dev_priv->display.init_clock_gating = broadwater_init_clock_gating;  in intel_init_pm()
6610 		dev_priv->display.update_wm = i9xx_update_wm;  in intel_init_pm()
6611 		dev_priv->display.get_fifo_size = i9xx_get_fifo_size;  in intel_init_pm()
6612 		dev_priv->display.init_clock_gating = gen3_init_clock_gating;  in intel_init_pm()
6615 			dev_priv->display.update_wm = i845_update_wm;  in intel_init_pm()
6616 			dev_priv->display.get_fifo_size = i845_get_fifo_size;  in intel_init_pm()
6618 			dev_priv->display.update_wm = i9xx_update_wm;  in intel_init_pm()
6619 			dev_priv->display.get_fifo_size = i830_get_fifo_size;  in intel_init_pm()
6623 			dev_priv->display.init_clock_gating = i85x_init_clock_gating;  in intel_init_pm()
6625 			dev_priv->display.init_clock_gating = i830_init_clock_gating;  in intel_init_pm()