923 	if (!intel_crtc->active || !plane->state->fb)  in vlv_compute_drain_latency()
961 	if (!crtc->active || !plane->base.state->fb)  in vlv_compute_wm()
1483 	bool active;  member
1491 	bool active;  member
1523 	if (!params->active || !params->pri.enabled)  in ilk_compute_pri_wm()
1551 	if (!params->active || !params->spr.enabled)  in ilk_compute_spr_wm()
1572 	if (!params->active || !params->cur.enabled)  in ilk_compute_cur_wm()
1586 	if (!params->active || !params->pri.enabled)  in ilk_compute_fbc_wm()
1786 	if (!intel_crtc->active)  in hsw_compute_linetime_wm()
2041 	if (!intel_crtc->active)  in ilk_compute_wm_parameters()
2044 	p->active = true;  in ilk_compute_wm_parameters()
2082 		const struct intel_pipe_wm *wm = &intel_crtc->wm.active;  in ilk_compute_wm_config()
2109 	pipe_wm->pipe_enabled = params->active;  in intel_compute_pipe_wm()
2166 		const struct intel_pipe_wm *active = &intel_crtc->wm.active;  in ilk_merge_wm_level()  local
2167 		const struct intel_wm_level *wm = &active->wm[level];  in ilk_merge_wm_level()
2169 		if (!active->pipe_enabled)  in ilk_merge_wm_level()
2314 			&intel_crtc->wm.active.wm[0];  in ilk_compute_wm_results()
2319 		results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;  in ilk_compute_wm_results()
2551 	if (!params->active) {  in skl_ddb_get_pipe_allocation_limits()
2563 		if (!to_intel_crtc(crtc)->active)  in skl_ddb_get_pipe_allocation_limits()
2803 		config->num_pipes_active += to_intel_crtc(crtc)->active;  in skl_compute_wm_global_parameters()
2824 	p->active = intel_crtc->active;  in skl_compute_wm_pipe_parameters()
2825 	if (p->active) {  in skl_compute_wm_pipe_parameters()
2880 	if (latency == 0 || !p->active || !p_params->enabled)  in skl_compute_plane_wm()
2974 	if (!to_intel_crtc(crtc)->active)  in skl_compute_linetime_wm()
2988 	if (!params->active)  in skl_compute_transition_wm()
3194 		if (!crtc->active)  in skl_flush_wm_values()
3217 		if (!crtc->active)  in skl_flush_wm_values()
3240 		if (!crtc->active)  in skl_flush_wm_values()
3305 		if (!intel_crtc->active)  in skl_update_other_pipe_wm()
3395 	if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))  in ilk_update_wm()
3398 	intel_crtc->wm.active = pipe_wm;  in ilk_update_wm()
3453 				     struct skl_pipe_wm *active,  in skl_pipe_wm_active_state()  argument
3463 			active->wm[level].plane_en[i] = is_enabled;  in skl_pipe_wm_active_state()
3464 			active->wm[level].plane_res_b[i] =  in skl_pipe_wm_active_state()
3466 			active->wm[level].plane_res_l[i] =  in skl_pipe_wm_active_state()
3470 			active->wm[level].cursor_en = is_enabled;  in skl_pipe_wm_active_state()
3471 			active->wm[level].cursor_res_b =  in skl_pipe_wm_active_state()
3473 			active->wm[level].cursor_res_l =  in skl_pipe_wm_active_state()
3479 			active->trans_wm.plane_en[i] = is_enabled;  in skl_pipe_wm_active_state()
3480 			active->trans_wm.plane_res_b[i] =  in skl_pipe_wm_active_state()
3482 			active->trans_wm.plane_res_l[i] =  in skl_pipe_wm_active_state()
3486 			active->trans_wm.cursor_en = is_enabled;  in skl_pipe_wm_active_state()
3487 			active->trans_wm.cursor_res_b =  in skl_pipe_wm_active_state()
3489 			active->trans_wm.cursor_res_l =  in skl_pipe_wm_active_state()
3502 	struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;  in skl_pipe_wm_get_hw_state()  local
3522 	if (!intel_crtc->active)  in skl_pipe_wm_get_hw_state()
3527 	active->linetime = hw->wm_linetime[pipe];  in skl_pipe_wm_get_hw_state()
3532 			skl_pipe_wm_active_state(temp, active, false,  in skl_pipe_wm_get_hw_state()
3536 		skl_pipe_wm_active_state(temp, active, false, true, i, level);  in skl_pipe_wm_get_hw_state()
3541 		skl_pipe_wm_active_state(temp, active, true, false, i, 0);  in skl_pipe_wm_get_hw_state()
3545 	skl_pipe_wm_active_state(temp, active, true, true, i, 0);  in skl_pipe_wm_get_hw_state()
3565 	struct intel_pipe_wm *active = &intel_crtc->wm.active;  in ilk_pipe_wm_get_hw_state()  local
3577 	memset(active, 0, sizeof(*active));  in ilk_pipe_wm_get_hw_state()
3579 	active->pipe_enabled = intel_crtc->active;  in ilk_pipe_wm_get_hw_state()
3581 	if (active->pipe_enabled) {  in ilk_pipe_wm_get_hw_state()
3590 		active->wm[0].enable = true;  in ilk_pipe_wm_get_hw_state()
3591 		active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;  in ilk_pipe_wm_get_hw_state()
3592 		active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;  in ilk_pipe_wm_get_hw_state()
3593 		active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;  in ilk_pipe_wm_get_hw_state()
3594 		active->linetime = hw->wm_linetime[pipe];  in ilk_pipe_wm_get_hw_state()
3604 			active->wm[level].enable = true;  in ilk_pipe_wm_get_hw_state()