Lines Matching refs:I915_WRITE
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | in gen9_init_clock_gating()
75 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in skl_init_clock_gating()
82 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | in skl_init_clock_gating()
86 I915_WRITE(FF_SLICE_CS_CHICKEN2, in skl_init_clock_gating()
93 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | in skl_init_clock_gating()
313 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); in intel_set_memory_cxsr()
317 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); in intel_set_memory_cxsr()
321 I915_WRITE(DSPFW3, val); in intel_set_memory_cxsr()
325 I915_WRITE(FW_BLC_SELF, val); in intel_set_memory_cxsr()
329 I915_WRITE(INSTPM, val); in intel_set_memory_cxsr()
668 I915_WRITE(DSPFW1, reg); in pineview_update_wm()
678 I915_WRITE(DSPFW3, reg); in pineview_update_wm()
687 I915_WRITE(DSPFW3, reg); in pineview_update_wm()
696 I915_WRITE(DSPFW3, reg); in pineview_update_wm()
850 I915_WRITE(VLV_DDL(pipe), in vlv_write_wm_values()
856 I915_WRITE(DSPFW1, in vlv_write_wm_values()
861 I915_WRITE(DSPFW2, in vlv_write_wm_values()
865 I915_WRITE(DSPFW3, in vlv_write_wm_values()
869 I915_WRITE(DSPFW7_CHV, in vlv_write_wm_values()
872 I915_WRITE(DSPFW8_CHV, in vlv_write_wm_values()
875 I915_WRITE(DSPFW9_CHV, in vlv_write_wm_values()
878 I915_WRITE(DSPHOWM, in vlv_write_wm_values()
890 I915_WRITE(DSPFW7, in vlv_write_wm_values()
893 I915_WRITE(DSPHOWM, in vlv_write_wm_values()
1165 I915_WRITE(DSPFW1, in g4x_update_wm()
1170 I915_WRITE(DSPFW2, in g4x_update_wm()
1174 I915_WRITE(DSPFW3, in g4x_update_wm()
1242 I915_WRITE(DSPFW1, FW_WM(srwm, SR) | in i965_update_wm()
1246 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) | in i965_update_wm()
1249 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); in i965_update_wm()
1365 I915_WRITE(FW_BLC_SELF, in i9xx_update_wm()
1368 I915_WRITE(FW_BLC_SELF, srwm & 0x3f); in i9xx_update_wm()
1381 I915_WRITE(FW_BLC, fwater_lo); in i9xx_update_wm()
1382 I915_WRITE(FW_BLC2, fwater_hi); in i9xx_update_wm()
1411 I915_WRITE(FW_BLC, fwater_lo); in i845_update_wm()
2424 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); in _ilk_disable_lp_wm()
2429 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); in _ilk_disable_lp_wm()
2434 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); in _ilk_disable_lp_wm()
2465 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); in ilk_write_wm_values()
2467 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); in ilk_write_wm_values()
2469 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); in ilk_write_wm_values()
2472 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); in ilk_write_wm_values()
2474 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); in ilk_write_wm_values()
2476 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); in ilk_write_wm_values()
2485 I915_WRITE(WM_MISC, val); in ilk_write_wm_values()
2492 I915_WRITE(DISP_ARB_CTL2, val); in ilk_write_wm_values()
2502 I915_WRITE(DISP_ARB_CTL, val); in ilk_write_wm_values()
2507 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); in ilk_write_wm_values()
2511 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); in ilk_write_wm_values()
2513 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); in ilk_write_wm_values()
2517 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); in ilk_write_wm_values()
2519 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); in ilk_write_wm_values()
2521 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); in ilk_write_wm_values()
3079 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); in skl_ddb_entry_write()
3081 I915_WRITE(reg, 0); in skl_ddb_entry_write()
3097 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); in skl_write_wm_values()
3101 I915_WRITE(PLANE_WM(pipe, i, level), in skl_write_wm_values()
3103 I915_WRITE(CUR_WM(pipe, level), in skl_write_wm_values()
3107 I915_WRITE(PLANE_WM_TRANS(pipe, i), in skl_write_wm_values()
3109 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]); in skl_write_wm_values()
3153 I915_WRITE(PLANE_SURF(pipe, plane), in skl_wm_flush_pipe()
3156 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); in skl_wm_flush_pipe()
3739 I915_WRITE(RCUPEI, 100000); in ironlake_enable_drps()
3740 I915_WRITE(RCDNEI, 100000); in ironlake_enable_drps()
3743 I915_WRITE(RCBMAXAVG, 90000); in ironlake_enable_drps()
3744 I915_WRITE(RCBMINAVG, 80000); in ironlake_enable_drps()
3746 I915_WRITE(MEMIHYST, 1); in ironlake_enable_drps()
3767 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); in ironlake_enable_drps()
3773 I915_WRITE(VIDSTART, vstart); in ironlake_enable_drps()
3777 I915_WRITE(MEMMODECTL, rgvmodectl); in ironlake_enable_drps()
3804 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); in ironlake_disable_drps()
3805 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); in ironlake_disable_drps()
3806 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); in ironlake_disable_drps()
3807 I915_WRITE(DEIIR, DE_PCU_EVENT); in ironlake_disable_drps()
3808 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); in ironlake_disable_drps()
3814 I915_WRITE(MEMSWCTL, rgvswctl); in ironlake_disable_drps()
3914 I915_WRITE(GEN6_RP_UP_EI, in gen6_set_rps_thresholds()
3916 I915_WRITE(GEN6_RP_UP_THRESHOLD, in gen6_set_rps_thresholds()
3919 I915_WRITE(GEN6_RP_DOWN_EI, in gen6_set_rps_thresholds()
3921 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, in gen6_set_rps_thresholds()
3924 I915_WRITE(GEN6_RP_CONTROL, in gen6_set_rps_thresholds()
3968 I915_WRITE(GEN6_RPNSWREQ, in gen6_set_rps()
3971 I915_WRITE(GEN6_RPNSWREQ, in gen6_set_rps()
3974 I915_WRITE(GEN6_RPNSWREQ, in gen6_set_rps()
3983 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); in gen6_set_rps()
3984 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); in gen6_set_rps()
4007 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); in valleyview_set_rps()
4041 I915_WRITE(GEN6_PMINTRMSK, in vlv_set_rps_idle()
4056 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); in vlv_set_rps_idle()
4065 I915_WRITE(GEN6_PMINTRMSK, in gen6_rps_busy()
4082 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); in gen6_rps_idle()
4114 I915_WRITE(GEN6_RC_CONTROL, 0); in gen9_disable_rps()
4115 I915_WRITE(GEN9_PG_ENABLE, 0); in gen9_disable_rps()
4122 I915_WRITE(GEN6_RC_CONTROL, 0); in gen6_disable_rps()
4123 I915_WRITE(GEN6_RPNSWREQ, 1 << 31); in gen6_disable_rps()
4130 I915_WRITE(GEN6_RC_CONTROL, 0); in cherryview_disable_rps()
4141 I915_WRITE(GEN6_RC_CONTROL, 0); in valleyview_disable_rps()
4271 I915_WRITE(GEN6_RC_VIDEO_FREQ, in gen9_enable_rps()
4275 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, in gen9_enable_rps()
4278 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); in gen9_enable_rps()
4297 I915_WRITE(GEN6_RC_STATE, 0); in gen9_enable_rc6()
4304 I915_WRITE(GEN6_RC_CONTROL, 0); in gen9_enable_rc6()
4307 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); in gen9_enable_rc6()
4308 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in gen9_enable_rc6()
4309 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in gen9_enable_rc6()
4311 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); in gen9_enable_rc6()
4312 I915_WRITE(GEN6_RC_SLEEP, 0); in gen9_enable_rc6()
4313 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ in gen9_enable_rc6()
4316 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); in gen9_enable_rc6()
4317 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); in gen9_enable_rc6()
4324 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | in gen9_enable_rc6()
4329 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 3 : 0); in gen9_enable_rc6()
4343 I915_WRITE(GEN6_RC_STATE, 0); in gen8_enable_rps()
4350 I915_WRITE(GEN6_RC_CONTROL, 0); in gen8_enable_rps()
4356 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); in gen8_enable_rps()
4357 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in gen8_enable_rps()
4358 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in gen8_enable_rps()
4360 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); in gen8_enable_rps()
4361 I915_WRITE(GEN6_RC_SLEEP, 0); in gen8_enable_rps()
4363 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ in gen8_enable_rps()
4365 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ in gen8_enable_rps()
4372 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | in gen8_enable_rps()
4376 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | in gen8_enable_rps()
4381 I915_WRITE(GEN6_RPNSWREQ, in gen8_enable_rps()
4383 I915_WRITE(GEN6_RC_VIDEO_FREQ, in gen8_enable_rps()
4386 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ in gen8_enable_rps()
4389 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, in gen8_enable_rps()
4393 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ in gen8_enable_rps()
4394 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ in gen8_enable_rps()
4395 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ in gen8_enable_rps()
4396 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ in gen8_enable_rps()
4398 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); in gen8_enable_rps()
4401 I915_WRITE(GEN6_RP_CONTROL, in gen8_enable_rps()
4434 I915_WRITE(GEN6_RC_STATE, 0); in gen6_enable_rps()
4439 I915_WRITE(GTFIFODBG, gtfifodbg); in gen6_enable_rps()
4448 I915_WRITE(GEN6_RC_CONTROL, 0); in gen6_enable_rps()
4450 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); in gen6_enable_rps()
4451 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); in gen6_enable_rps()
4452 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); in gen6_enable_rps()
4453 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); in gen6_enable_rps()
4454 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); in gen6_enable_rps()
4457 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); in gen6_enable_rps()
4459 I915_WRITE(GEN6_RC_SLEEP, 0); in gen6_enable_rps()
4460 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); in gen6_enable_rps()
4462 I915_WRITE(GEN6_RC6_THRESHOLD, 125000); in gen6_enable_rps()
4464 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); in gen6_enable_rps()
4465 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); in gen6_enable_rps()
4466 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ in gen6_enable_rps()
4484 I915_WRITE(GEN6_RC_CONTROL, in gen6_enable_rps()
4490 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); in gen6_enable_rps()
4491 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); in gen6_enable_rps()
4762 I915_WRITE(VLV_PCBR, pctx_paddr); in cherryview_setup_pctx()
4808 I915_WRITE(VLV_PCBR, pctx_paddr); in valleyview_setup_pctx()
4978 I915_WRITE(GTFIFODBG, gtfifodbg); in cherryview_enable_rps()
4988 I915_WRITE(GEN6_RC_CONTROL, 0); in cherryview_enable_rps()
4991 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); in cherryview_enable_rps()
4992 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ in cherryview_enable_rps()
4993 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ in cherryview_enable_rps()
4996 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); in cherryview_enable_rps()
4997 I915_WRITE(GEN6_RC_SLEEP, 0); in cherryview_enable_rps()
5000 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); in cherryview_enable_rps()
5003 I915_WRITE(VLV_COUNTER_CONTROL, in cherryview_enable_rps()
5016 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); in cherryview_enable_rps()
5019 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); in cherryview_enable_rps()
5020 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); in cherryview_enable_rps()
5021 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); in cherryview_enable_rps()
5022 I915_WRITE(GEN6_RP_UP_EI, 66000); in cherryview_enable_rps()
5023 I915_WRITE(GEN6_RP_DOWN_EI, 350000); in cherryview_enable_rps()
5025 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); in cherryview_enable_rps()
5028 I915_WRITE(GEN6_RP_CONTROL, in cherryview_enable_rps()
5071 I915_WRITE(GTFIFODBG, gtfifodbg); in valleyview_enable_rps()
5078 I915_WRITE(GEN6_RC_CONTROL, 0); in valleyview_enable_rps()
5080 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); in valleyview_enable_rps()
5081 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); in valleyview_enable_rps()
5082 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); in valleyview_enable_rps()
5083 I915_WRITE(GEN6_RP_UP_EI, 66000); in valleyview_enable_rps()
5084 I915_WRITE(GEN6_RP_DOWN_EI, 350000); in valleyview_enable_rps()
5086 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); in valleyview_enable_rps()
5088 I915_WRITE(GEN6_RP_CONTROL, in valleyview_enable_rps()
5096 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); in valleyview_enable_rps()
5097 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); in valleyview_enable_rps()
5098 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); in valleyview_enable_rps()
5101 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); in valleyview_enable_rps()
5103 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); in valleyview_enable_rps()
5106 I915_WRITE(VLV_COUNTER_CONTROL, in valleyview_enable_rps()
5117 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); in valleyview_enable_rps()
5566 I915_WRITE(ECR, 0); in intel_init_emon()
5570 I915_WRITE(SDEW, 0x15040d00); in intel_init_emon()
5571 I915_WRITE(CSIEW0, 0x007f0000); in intel_init_emon()
5572 I915_WRITE(CSIEW1, 0x1e220004); in intel_init_emon()
5573 I915_WRITE(CSIEW2, 0x04000004); in intel_init_emon()
5576 I915_WRITE(PEW + (i * 4), 0); in intel_init_emon()
5578 I915_WRITE(DEW + (i * 4), 0); in intel_init_emon()
5603 I915_WRITE(PXW + (i * 4), val); in intel_init_emon()
5607 I915_WRITE(OGW0, 0); in intel_init_emon()
5608 I915_WRITE(OGW1, 0); in intel_init_emon()
5609 I915_WRITE(EG0, 0x00007f00); in intel_init_emon()
5610 I915_WRITE(EG1, 0x0000000e); in intel_init_emon()
5611 I915_WRITE(EG2, 0x000e0000); in intel_init_emon()
5612 I915_WRITE(EG3, 0x68000300); in intel_init_emon()
5613 I915_WRITE(EG4, 0x42000000); in intel_init_emon()
5614 I915_WRITE(EG5, 0x00140031); in intel_init_emon()
5615 I915_WRITE(EG6, 0); in intel_init_emon()
5616 I915_WRITE(EG7, 0); in intel_init_emon()
5619 I915_WRITE(PXWL + (i * 4), 0); in intel_init_emon()
5622 I915_WRITE(ECR, 0x80000019); in intel_init_emon()
5795 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); in ibx_init_clock_gating()
5804 I915_WRITE(DSPCNTR(pipe), in g4x_disable_trickle_feed()
5815 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); in ilk_init_lp_watermarks()
5816 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); in ilk_init_lp_watermarks()
5817 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); in ilk_init_lp_watermarks()
5838 I915_WRITE(PCH_3DCGDIS0, in ironlake_init_clock_gating()
5841 I915_WRITE(PCH_3DCGDIS1, in ironlake_init_clock_gating()
5851 I915_WRITE(ILK_DISPLAY_CHICKEN2, in ironlake_init_clock_gating()
5855 I915_WRITE(DISP_ARB_CTL, in ironlake_init_clock_gating()
5870 I915_WRITE(ILK_DISPLAY_CHICKEN1, in ironlake_init_clock_gating()
5873 I915_WRITE(ILK_DISPLAY_CHICKEN2, in ironlake_init_clock_gating()
5878 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); in ironlake_init_clock_gating()
5880 I915_WRITE(ILK_DISPLAY_CHICKEN2, in ironlake_init_clock_gating()
5883 I915_WRITE(_3D_CHICKEN2, in ironlake_init_clock_gating()
5888 I915_WRITE(CACHE_MODE_0, in ironlake_init_clock_gating()
5892 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in ironlake_init_clock_gating()
5910 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | in cpt_init_clock_gating()
5913 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | in cpt_init_clock_gating()
5927 I915_WRITE(TRANS_CHICKEN2(pipe), val); in cpt_init_clock_gating()
5931 I915_WRITE(TRANS_CHICKEN1(pipe), in cpt_init_clock_gating()
5952 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); in gen6_init_clock_gating()
5954 I915_WRITE(ILK_DISPLAY_CHICKEN2, in gen6_init_clock_gating()
5959 I915_WRITE(_3D_CHICKEN, in gen6_init_clock_gating()
5963 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in gen6_init_clock_gating()
5973 I915_WRITE(GEN6_GT_MODE, in gen6_init_clock_gating()
5978 I915_WRITE(CACHE_MODE_0, in gen6_init_clock_gating()
5981 I915_WRITE(GEN6_UCGCTL1, in gen6_init_clock_gating()
5999 I915_WRITE(GEN6_UCGCTL2, in gen6_init_clock_gating()
6004 I915_WRITE(_3D_CHICKEN3, in gen6_init_clock_gating()
6012 I915_WRITE(_3D_CHICKEN3, in gen6_init_clock_gating()
6026 I915_WRITE(ILK_DISPLAY_CHICKEN1, in gen6_init_clock_gating()
6029 I915_WRITE(ILK_DISPLAY_CHICKEN2, in gen6_init_clock_gating()
6032 I915_WRITE(ILK_DSPCLK_GATE_D, in gen6_init_clock_gating()
6059 I915_WRITE(GEN7_FF_THREAD_MODE, reg); in gen7_setup_fixed_func_scheduler()
6071 I915_WRITE(SOUTH_DSPCLK_GATE_D, in lpt_init_clock_gating()
6076 I915_WRITE(_TRANSA_CHICKEN1, in lpt_init_clock_gating()
6089 I915_WRITE(SOUTH_DSPCLK_GATE_D, val); in lpt_suspend_hw()
6098 I915_WRITE(WM3_LP_ILK, 0); in broadwell_init_clock_gating()
6099 I915_WRITE(WM2_LP_ILK, 0); in broadwell_init_clock_gating()
6100 I915_WRITE(WM1_LP_ILK, 0); in broadwell_init_clock_gating()
6103 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); in broadwell_init_clock_gating()
6106 I915_WRITE(CHICKEN_PAR1_1, in broadwell_init_clock_gating()
6111 I915_WRITE(CHICKEN_PIPESL_1(pipe), in broadwell_init_clock_gating()
6118 I915_WRITE(GEN7_FF_THREAD_MODE, in broadwell_init_clock_gating()
6122 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, in broadwell_init_clock_gating()
6126 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in broadwell_init_clock_gating()
6139 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); in haswell_init_clock_gating()
6140 I915_WRITE(HSW_ROW_CHICKEN3, in haswell_init_clock_gating()
6144 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, in haswell_init_clock_gating()
6149 I915_WRITE(GEN7_FF_THREAD_MODE, in haswell_init_clock_gating()
6153 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in haswell_init_clock_gating()
6156 I915_WRITE(CACHE_MODE_0_GEN7, in haswell_init_clock_gating()
6160 I915_WRITE(CACHE_MODE_1, in haswell_init_clock_gating()
6171 I915_WRITE(GEN7_GT_MODE, in haswell_init_clock_gating()
6175 I915_WRITE(HALF_SLICE_CHICKEN3, in haswell_init_clock_gating()
6179 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); in haswell_init_clock_gating()
6182 I915_WRITE(CHICKEN_PAR1_1, in haswell_init_clock_gating()
6195 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); in ivybridge_init_clock_gating()
6198 I915_WRITE(_3D_CHICKEN3, in ivybridge_init_clock_gating()
6202 I915_WRITE(IVB_CHICKEN3, in ivybridge_init_clock_gating()
6208 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, in ivybridge_init_clock_gating()
6212 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in ivybridge_init_clock_gating()
6215 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, in ivybridge_init_clock_gating()
6219 I915_WRITE(GEN7_L3CNTLREG1, in ivybridge_init_clock_gating()
6221 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, in ivybridge_init_clock_gating()
6224 I915_WRITE(GEN7_ROW_CHICKEN2, in ivybridge_init_clock_gating()
6228 I915_WRITE(GEN7_ROW_CHICKEN2, in ivybridge_init_clock_gating()
6230 I915_WRITE(GEN7_ROW_CHICKEN2_GT2, in ivybridge_init_clock_gating()
6235 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & in ivybridge_init_clock_gating()
6242 I915_WRITE(GEN6_UCGCTL2, in ivybridge_init_clock_gating()
6246 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, in ivybridge_init_clock_gating()
6256 I915_WRITE(CACHE_MODE_0_GEN7, in ivybridge_init_clock_gating()
6261 I915_WRITE(CACHE_MODE_1, in ivybridge_init_clock_gating()
6272 I915_WRITE(GEN7_GT_MODE, in ivybridge_init_clock_gating()
6278 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); in ivybridge_init_clock_gating()
6288 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); in vlv_init_display_clock_gating()
6293 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); in vlv_init_display_clock_gating()
6294 I915_WRITE(CBR1_VLV, 0); in vlv_init_display_clock_gating()
6304 I915_WRITE(_3D_CHICKEN3, in valleyview_init_clock_gating()
6308 I915_WRITE(IVB_CHICKEN3, in valleyview_init_clock_gating()
6314 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, in valleyview_init_clock_gating()
6319 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in valleyview_init_clock_gating()
6322 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & in valleyview_init_clock_gating()
6326 I915_WRITE(GEN7_ROW_CHICKEN2, in valleyview_init_clock_gating()
6330 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, in valleyview_init_clock_gating()
6340 I915_WRITE(GEN6_UCGCTL2, in valleyview_init_clock_gating()
6346 I915_WRITE(GEN7_UCGCTL4, in valleyview_init_clock_gating()
6353 I915_WRITE(CACHE_MODE_1, in valleyview_init_clock_gating()
6364 I915_WRITE(GEN7_GT_MODE, in valleyview_init_clock_gating()
6371 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); in valleyview_init_clock_gating()
6378 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); in valleyview_init_clock_gating()
6389 I915_WRITE(GEN7_FF_THREAD_MODE, in cherryview_init_clock_gating()
6394 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, in cherryview_init_clock_gating()
6398 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | in cherryview_init_clock_gating()
6402 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in cherryview_init_clock_gating()
6411 I915_WRITE(RENCLK_GATE_D1, 0); in g4x_init_clock_gating()
6412 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | in g4x_init_clock_gating()
6415 I915_WRITE(RAMCLK_GATE_D, 0); in g4x_init_clock_gating()
6421 I915_WRITE(DSPCLK_GATE_D, dspclk_gate); in g4x_init_clock_gating()
6424 I915_WRITE(CACHE_MODE_0, in g4x_init_clock_gating()
6428 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in g4x_init_clock_gating()
6437 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); in crestline_init_clock_gating()
6438 I915_WRITE(RENCLK_GATE_D2, 0); in crestline_init_clock_gating()
6439 I915_WRITE(DSPCLK_GATE_D, 0); in crestline_init_clock_gating()
6440 I915_WRITE(RAMCLK_GATE_D, 0); in crestline_init_clock_gating()
6442 I915_WRITE(MI_ARB_STATE, in crestline_init_clock_gating()
6446 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in crestline_init_clock_gating()
6453 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | in broadwater_init_clock_gating()
6458 I915_WRITE(RENCLK_GATE_D2, 0); in broadwater_init_clock_gating()
6459 I915_WRITE(MI_ARB_STATE, in broadwater_init_clock_gating()
6463 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); in broadwater_init_clock_gating()
6473 I915_WRITE(D_STATE, dstate); in gen3_init_clock_gating()
6476 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); in gen3_init_clock_gating()
6479 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); in gen3_init_clock_gating()
6482 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); in gen3_init_clock_gating()
6485 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); in gen3_init_clock_gating()
6487 I915_WRITE(MI_ARB_STATE, in gen3_init_clock_gating()
6495 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); in i85x_init_clock_gating()
6498 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | in i85x_init_clock_gating()
6501 I915_WRITE(MEM_MODE, in i85x_init_clock_gating()
6509 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); in i830_init_clock_gating()
6511 I915_WRITE(MEM_MODE, in i830_init_clock_gating()
6640 I915_WRITE(GEN6_PCODE_DATA, *val); in sandybridge_pcode_read()
6641 I915_WRITE(GEN6_PCODE_DATA1, 0); in sandybridge_pcode_read()
6642 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); in sandybridge_pcode_read()
6651 I915_WRITE(GEN6_PCODE_DATA, 0); in sandybridge_pcode_read()
6665 I915_WRITE(GEN6_PCODE_DATA, val); in sandybridge_pcode_write()
6666 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); in sandybridge_pcode_write()
6674 I915_WRITE(GEN6_PCODE_DATA, 0); in sandybridge_pcode_write()