593 	entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);  in intel_calculate_wm()
738 	entries = DIV_ROUND_UP(entries, display->cacheline_size);  in g4x_compute_wm0()
750 	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);  in g4x_compute_wm0()
828 	entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);  in g4x_compute_srwm()
833 	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);  in g4x_compute_srwm()
934 	entries = DIV_ROUND_UP(clock, 1000) * pixel_size;  in vlv_compute_drain_latency()
967 	entries = DIV_ROUND_UP(clock, 1000) * pixel_size;  in vlv_compute_wm()
978 	return fifo_size - clamp(DIV_ROUND_UP(256 * entries, 64), 0, fifo_size - 8);  in vlv_compute_wm()
1210 		entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);  in i965_update_wm()
1220 		entries = DIV_ROUND_UP(entries,  in i965_update_wm()
1358 		entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);  in i9xx_update_wm()
1472 	ret = DIV_ROUND_UP(ret, 64) + 2;  in ilk_wm_method2()
1479 	return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;  in ilk_wm_fbc()
1976 		wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));  in ilk_increase_wm_latency()
2743 	ret = DIV_ROUND_UP(wm_intermediate_val, 1000);  in skl_wm_method1()
2764 		plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);  in skl_wm_method2()
2767 		plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);  in skl_wm_method2()
2771 	ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *  in skl_wm_method2()
2895 	plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);  in skl_compute_plane_wm()
2923 	res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);  in skl_compute_plane_wm()
2977 	return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);  in skl_compute_linetime_wm()